Neural nets supplied synapse signals obtained by digital-to-analog conversion of plural-bit samples

• US 5,247,605 A
• Filed: 12/13/1991
• Issued: 09/21/1993
• Est. Priority Date: 07/02/1990
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Engeler, William E.
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): DAVIS, GEORGE B
• Application Number:
  US07/807,619
• Time in Patent Office: 648 Days
• Field of Search: 395/24, 395/27, 364/807, 364/754
• US Class Current: 706/22
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology

Abstract

Digital synapse input signals which are temporally aligned with each other are converted to analog form for application to a neural net layer. Several digital synapse input signals can be written into digital memory at different times, to be read out in temporal alignment for conversion to analog form for application to a neural net layer. The digital synapse input signals can originate from apparatus for raster-scanning a field or successive fields of video samples, for example, with the neural net layer providing filters for recognizing shapes in a field of the video samples. The neural net layer can be either a pre-programmed type or a learning type, and its axonal outputs may be digitized for use in subsequent digital processing.

Claims

1. A system comprising:

means for generating in serial order sets of P temporally aligned digital input signal samples, P being an integer greater than one, each of which temporarily aligned digital input signal samples has a plurality of bits B in number, each of which bits has one of two conditions which two conditions are represented by respective electric signal levels;

means for converting each set of P temporally aligned digital input signal samples to a corresponding set of temporally aligned analog input signal samples, which means for converting includes

a plurality P in number of digital-to-analog converters, each for converting a respective one of said P temporally aligned digital input signal samples to a corresponding one of said temporally aligned analog input signal samples; and

a neural net layer, responsive to said corresponding sets of P temporally aligned analog input signal samples being applied thereto as synapse input signals, for generating in serial order respective analog samples of each of a number M of axonal output signals.

2. A system as set forth in claim 1 including:

means for digitizing each analog sample of said M respective axonal output responses.

3. A system comprising:

means for generating in serial order sets of P temporally aligned digital input signal samples, P being an integer greater than one;

means for converting each plurality Q in number of sets of P temporally aligned digital input signal samples most recently generated, as obtains each time a new one of said sets of P temporally aligned digital input signal samples is generated, to a corresponding group of temporally aligned analog input signal samples P times Q in number; and

a neural net layer, responsive to said groups of temporally aligned analog input signal samples applied thereto as synapse input signals, for generating in serial order respective analog samples of each of a number M of axonal output signals.

4. A system as set forth in claim 3 including:

means for digitizing each analog sample of said M respective axonal output responses.

5. A system as set forth in claim 3 wherein said said means for converting includes:

a plurality, P in number, of serial-in/parallel-out registers, each operative as digital tapped delay line having Q output taps for supplying Q respective output signals, and each receiving as a serial input signal thereto a respective one of each set of said most recently generated P temporally aligned digital input signal samples, whereby groups of temporally aligned digital input signal samples P times Q in number are generated one after another; and

a plurality, P times Q in number, of digital-to-analog converters for generating in parallel said groups of temporally aligned analog input signal samples P times Q in number applied as synapse input signals to said neural net layer, said generating in parallel being carried out responsive to said groups of temporally aligned digital input signal samples P times Q in number generated one after another from the output taps of said P serial-in/parallel-out registers.

6. A system as set forth in claim 3 wherein said said means for converting includes:

a plurality, P in number, of digital-to-analog converters, each for converting a respective stream the temporally aligned digital input signal samples from each said new set thereof to a corresponding stream of analog input signal samples; and

a plurality, P in number, of analog tapped delay lines, each receiving a respective said corresponding stream of analog input signal samples from a respective one of said digital-to-analog converters and having a plurality Q in number of taps at single-sample intervals from which each successive said group of temporally aligned analog input signal samples P times Q in number is supplied, to provide synapse input signals to said neural net layer.

7. A system including a neural net layer, said system comprising:

apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples, to generate M respective weighted summation results, being included in said neural net layer;

circuitry for supplying a plurality P in number of streams of digital samples manifested in electric signal form, said streams of digital samples being herein and hereafter identified by respective ones of the consecutive numbers first through P^th, the samples in each of said first through P^th streams being supplied in a respective serial order;

digital-to-analog conversion apparatus for generating groups of temporally aligned analog input signal samples, each said group of temporally aligned analog input signal samples being generated responsive to the plurality Q in number of most recently supplied samples in each of said first through P^th streams of successive digital samples, and each said group of temporally aligned analog input signal samples being supplied as temporally aligned analog synapse input signal samples to said apparatus for performing a number M of weighted summations in the analog regime; and

circuitry included in said neural net layer for non-linearly processing said M respective weighted summation results to obtain respective axonal output responses.

8. A system as set forth in claim 7 including:

analog-to-digital conversion apparatus for digitizing each of said M respective axonal output responses.

9. A system as set forth in claim 7 wherein said circuitry for supplying a plurality P in number of streams of digital samples comprises:

an electronic memory separated into P portions for reading in parallel to generate ones of said first through P^th streams of successive digital samples; and

circuitry for writing digital samples into said electronic memory.

10. A system as set forth in claim 9 wherein said digital-to-analog conversion apparatus comprises:

circuitry for digit-slicing each of the digital samples in the plurality Q in number of most recently supplied samples in each of said first through P^th streams of digital samples, thereby to generate a plurality D in number of corresponding digits herein and hereafter identified by respective ones of the consecutive ordinal numbers first through D^th, the digits identified by the same ordinal number constituting a digital slice of corresponding ordinal number; and

circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices.

11. A system as set forth in claim 10 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

apparatus for performing a number M of partial weighted summations in the analog regime of signal samples comprising each digit slice of said group of temporally aligned analog input signal samples, thereby to generate D respective sets of M partial weighted summation results; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation result in said sets of M partial weighted summation results, thereby to generate M respective final weighted summation results.

12. A system as set forth in claim 10 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

first through D^th pluralities, each P times Q in number, of digital-to-analog converters for generating in parallel said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

13. A system as set forth in claim 12 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a plurality, D in number, of first through D^th weighted summation networks for respectively performing M weighted summations in the analog regime of temporally aligned analog input signal samples converted from said first through D^th digit slices respectively by said first through Dth pluralities, each P times Q in number, of digital-to-analog converters, thereby generating D corresponding groups of M partial weighted summation results; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation results in said groups of M partial weighted summation results being of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are parallelly summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those corresponding partial weighted summations arise.

14. A system as set forth in claim 10 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

a single plurality P times Q in number, of digital-to-analog converters for generating in sequence said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

15. A system as set forth in claim 14 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a weighted summation network for performing M weighted summations in the analog regime of temporally aligned analog input signal samples sequentially converted from said first through D^th digit slices by said plurality of digital-to-analog converters, thereby to generate in serial order D sets of M partial summation results; and

apparatus for performing final weighted summations of said D sets of M partial weighted summation results, which apparatus is of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are sequentially summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those D corresponding partial weighted summation results arise.

16. A system as set forth in claim 9 including:

analog-to-digital conversion apparatus for digitizing each of said M respective axonal output responses.

17. A system as set forth in claim 7 wherein said circuitry for supplying a plurality P in number of streams of digital samples comprises:

a source of digital samples supplied in serial order and manifested in electric signal form describing the raster scanning of a number of fields of data, each of which fields extends over two dimensions in space;

an electronic memory for providing a tapped digital delay line for said successive digital samples, which tapped digital delay line has a plurality P in number of taps at single-scan-line intervals in said raster scanning for respectively supplying said first through P^th streams of digital samples.

18. A system as set forth in claim 17 wherein said digital-to-analog conversion apparatus comprises:

circuitry for digit-slicing each of the digital samples in the plurality Q in number of most recently supplied samples in each of said first through P^th streams of digital samples, thereby to generate a plurality D in number of corresponding digits herein and hereafter identified by respective ones of the consecutive ordinal numbers first through D^th, the digits identified by the same ordinal number constituting a digital slice of corresponding ordinal number; and

circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices.

19. A system as set forth in claim 18 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

apparatus for performing a number M of partial weighted summations in the analog regime of signal samples comprising each digit slice of said set of temporally aligned analog input signal samples, thereby to generate D respective sets of M partial weighted summation results; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation results in said sets of M partial weighted summation results, thereby to generate M respective final weighted summation results.

20. A system as set forth in claim 18 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

first through Dth pluralities, each P times Q in number, of digital-to-analog converters for generating in parallel said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

21. A system as set forth in claim 20 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a plurality, D in number, of first through D^th weighted summation networks for respectively performing M weighted summations in the analog regime of temporally aligned analog input signal samples converted from said first through D^th digit slices respectively by said first through Dth pluralities, each P times Q in number, of digital-to-analog converters, thereby generating D corresponding groups of M partial weighted summation results; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation results in said groups of M partial weighted summation results being of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are parallelly summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those corresponding partial weighted summations arise.

22. A system as set forth in claim 17 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

a single plurality P times Q in number, of digital-to-analog converters for generating in sequence said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

23. A system as set forth in claim 22 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a weighted summation network for performing M weighted summations in the analog regime of temporally aligned analog input signal samples sequentially converted from said first through D^th digit slices by said plurality of digital-to-analog converters, thereby to generate in serial order D sets of M partial summation results; and

apparatus for performing final weighted summations of said D sets of M partial weighted summation results, which apparatus is of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are sequentially summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those D corresponding partial weighted summation results arise.

24. A system as set forth in claim 17 including:

analog-to-digital conversion apparatus for digitizing each of said M respective axonal output responses.

25. A system as set forth in claim 17 wherein said digital-to-analog conversion apparatus comprises:

an array, P in number, of serial-in/parallel-out registers, each receiving successive digital input samples serially from a respective one of the P taps of said tapped digital delay line, temporarily storing the Q digital input samples most recently received serially from said source of successive digital samples, and supplying those Q temporarily stored digital input samples in temporal alignment; and

a plurality, P times Q in number, of digital-to-analog converters for converting respective ones of each of the respective Q temporally aligned digital samples temporarily stored in each of said serial-in/parallel-out registers to respective ones of said successive sets of temporally aligned analog input signal samples.

26. A system as set forth in claim 25 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

a single plurality P times Q in number, of digital-to-analog converters for generating in sequence said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

27. A system as set forth in claim 26 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a weighted summation network for performing M weighted summations in the analog regime of temporally aligned analog input signal samples sequentially converted from said first through D^th digit slices by said plurality of digital-to-analog converters, thereby to generate in serial order D sets of M partial summation results; and

apparatus for performing final weighted summations of said D sets of M partial weighted summation results, which apparatus is of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are sequentially summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those D corresponding partial weighted summation results arise.

28. A system as set forth in claim 25 including:

analog-to-digital conversion apparatus for digitizing each of said M respective axonal output responses.

29. A system as set forth in claim 17 wherein said digital-to-analog conversion apparatus comprises:

an array, P in number, of serial-in/parallel-out registers, each receiving successive digital input samples serially from a respective one of the P taps of said tapped digital delay line, temporarily storing the Q digital input samples most recently received serially from said source of successive digital samples, and supplying those Q temporarily stored digital input samples in temporal alignment;

circuitry for digit-slicing each of the Q digital samples temporarily stored in said array of serial-in/parallel-out registers, thereby to generate a plurality D in number of corresponding digits herein and hereafter identified by respective ones of the consecutive ordinal numbers first through D^th, the digits identified by the same ordinal number constituting a digital slice of corresponding ordinal number; and

circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices.

30. A system as set forth in claim 29 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

apparatus for performing a number M of partial weighted summations in the analog regime of signal samples comprising each digit slice of said set of temporally aligned analog input signal samples, thereby to generate D respective sets of M partial weighted summation results, one for each digit slice; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation results in said sets of M partial weighted summation results, thereby to generate M respective final weighted summation results.

31. A system as set forth in claim 29 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

first through Dth pluralities, each P times Q in number, of digital-to-analog converters for generating in parallel said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

32. A system as set forth in claim 31 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a plurality, D in number, of first through D^th weighted summation networks for respectively performing M weighted summations in the analog regime of temporally aligned analog input signal samples converted from said first through D^th digit slices respectively by said first through Dth pluralities, each P times Q in number, of digital-to-analog converters, thereby generating D corresponding groups of M partial weighted summation results; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation results in said groups of M partial weighted summation results being of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are parallelly summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those corresponding partial weighted summations arise.

33. A system as set forth in claim 17 characterized by said digital-to-analog conversion apparatus comprising:

a plurality, P in number, of digital-to-analog converters, each for converting a respective one of said first through P^th streams of digital samples to a corresponding stream of analog input signal samples manifested in electric signal form and supplied in serial order; and

a plurality, P in number, of analog tapped delay lines, each receiving from a respective one of said digital-to-analog converters said stream of analog input signal samples it supplies in serial order and having a plurality Q in number of taps at single-sample intervals from which each said group of temporally aligned analog input signal samples is supplied to said apparatus for performing a number M of weighted summations in the analog regime.

34. A system as set forth in claim 7 wherein said digital-to-analog conversion apparatus comprises:

circuitry for digit-slicing each of the digital samples in the plurality Q in number of most recently supplied samples in each of said first through P^th streams of digital samples, thereby to generate a plurality D in number of corresponding digits herein and hereafter identified by respective ones of the consecutive ordinal numbers first through D^th, the digits identified by the same ordinal number constituting a digital slice of corresponding ordinal number; and

circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices.

35. A system as set forth in claim 34 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

apparatus for performing a number M of partial weighted summations in the analog regime of signal samples comprising each digit slice of said group of temporally aligned analog input signal samples, thereby to generate D respective sets of M partial weighted summation results; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation results in said sets of M partial weighted summation results, thereby to generate M respective final weighted summation results.

36. A system as set forth in claim 34 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

first through D^th pluralities, each P times Q in number, of digital-to-analog converters for generating in parallel said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

37. A system as set forth in claim 36 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a plurality, D in number, of first through D^th weighted summation networks for respectively performing M weighted summations in the analog regime of temporally aligned analog input signal samples converted from said first through D^th digit slices respectively by said first through Dth pluralities, each P times Q in number, of digital-to-analog converters, thereby generating D corresponding groups of M partial weighted summation results; and

apparatus for performing final weighted summations of the D corresponding partial weighted summation results in said groups of M partial weighted summation results being of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are parallelly summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those corresponding partial weighted summations arise.

38. A system as set forth in claim 34 wherein said circuitry for generating a respective one of said groups of temporally aligned analog input signal samples responsive to each of said first through D^th digit slices is of a type including

a single plurality, P times Q in number, of digital-to-analog converters for generating in sequence said groups of temporally aligned analog input signal samples respectively responsive to first through D^th digit slices.

39. A system as set forth in claim 38 wherein said apparatus for performing a number M of weighted summations in the analog regime of temporally aligned analog synapse input signal samples comprises:

a weighted summation network for performing M weighted summations in the analog regime of temporally aligned analog input signal samples sequentially converted from said first through D^th digit slices by said plurality of digital-to-analog converters, thereby to generate in serial order D sets of M partial summation results; and

apparatus for performing final weighted summations of said D sets of M partial weighted summation results, which apparatus is of a type wherein the D corresponding partial weighted summation results in said sets of M partial weighted summation results are sequentially summed in the analog regime with respective weightings in accordance with the significance of the digit slice from which those D corresponding partial weighted summation results arise.

40. A system as set forth in claim 34 including:

analog-to-digital conversion apparatus for digitizing each of said M respective axonal output responses.