Sleep mode refresh apparatus

• US 5,247,655 A
• Filed: 11/07/1989
• Issued: 09/21/1993
• Est. Priority Date: 11/07/1989
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Inventors: Chen, Cheng, Khan, Rashid N., Cheng, Win-Sheng, Cheng, Chien-Feng, Gollabinnie, Aurav, Verstegen, Brian
• Primary Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US07/432,680
• Time in Patent Office: 1,414 Days
• Field of Search: 365/222, 365/227, 365/228, 365/229, 395/550, 395/750, 395/425, 371/16.3, 371/14, 364/200 MS File, 364/900 MS File
• US Class Current: 711/106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A circuit for waking a microprocessor from a sleep mode and providing it with its microprocessor clock long enough for a refresh, direct memory access (DMA) or master cycle operation to be done by external circuitry. The clock signal is then removed from the microprocessor to put it back into the sleep mode, thereby conserving energy. A hold signal is provided to the microprocessor to cause the microprocessor outputs to be put into a tri-state, high impedance condition, and thus relinquish control of the external bus to the external refreshing circuitry.

Claims

1. A circuit for putting a system into a state wherein dynamic memory can be refreshed during a sleep mode wherein a clock frequency of a microprocessor is reduced, said system having said microprocessor and separate refreshing circuitry coupled to said memory by an address bus said microprocessor having a lock input and a hold input, said microprocessor being operative to cause internal circuitry coupled to said address bus to enter a tri-state, high impedance condition in response to a signal on said hold input, said circuit comprising:

means for providing a system clock to elements other than said microprocessor in said system;

means for selectively providing a microprocessor clock having a sleep frequency for said sleep mode or an awake frequency greater than said sleep frequency to said clock input of said microprocessor; and

means, responsive to a control signal indicating a refresh operation, for providing said hold signal to said microprocessor and selecting said awake frequency from said means for providing a microprocessor clock.

2. The circuit of claim 1 wherein said control signal is an OR function of a refresh request signal, a DMA signal, and a master cycle signal.

3. The circuit of claim 1 further comprising means for activating and deactivating said microprocessor clock during a second phase of an external divided-down clock which is a duplicate of a divided-down clock internal to said microprocessor, said external divided-down clock and said system clock both originating from an external clock.

4. The circuit of claim 1 wherein said means for providing said hole signal and selecting said awake frequency also provided said hold signal and selects said awake frequency in response to an interrupt signal or a non-maskable interrupt signal.

5. The circuit of claim 1 wherein said means for providing said hold signal and selecting said awake frequency includes means for selecting said sleep frequency in response to detection of a halt signal.

6. The circuit of claim 1 wherein said means for selectively providing comprises a multiplexer for selecting either said sleep frequency or said awake frequency.

7. The circuit of claim 6 further comprising a second multiplexer for providing one of a plurality of sleep frequencies.

8. The circuit of claim 7 further comprising a first and a second means for providing different divided frequencies from an external clock frequency to a first and a second input of said second multiplexer.

9. A circuit for enabling the refreshing of a dynamic memory during a sleep mode in a system having a microprocessor coupled to said memory by an address bus, said microprocessor having a clock input and a hold input, said microprocessor being operative to cause internal circuitry coupled to said address bus to enter a tri-state, high impedance condition in response to a signal on said hold input, said circuit comprising:

a first multiplexer for providing either a sleep clock input or an awake clock input to said microprocessor clock input;

a register for storing a bit enabling a sleep mode;

first logic means for providing a sleep enable signal to a select input of said first multiplexer in response to an output of said register and a halt signal;

second logic means for providing an awake enable signal to a select input of said first multiplexer in response to a refresh, DMA or master cycle signal;

third logic means for generating a hold signal to said hold input of said microprocessor in response to said refresh, DMA or master cycle signal; and

fourth logic means for providing an awake signal to said select input of said first multiplexer in response to an interrupt signal.

10. The circuit of claim 9 further comprising a second multiplexer for selecting one of a plurality of sleep frequencies as an input to said first multiplexer.

11. The circuit of claim 10 further comprising a plurality of divide circuits coupled to an external clock for providing a plurality of divided-down clock frequency signals to said second multiplexer.

12. The circuit of claim 9 further comprising a second multiplexer coupled to said awake input of said first multiplexer for providing one of a plurality of clock frequencies.

13. The circuit of claim 9 further comprising means for synchronizing said sleep and awake signals to the phase of a divided-down version of said microprocessor clock signal.