Method and apparatus for controlling a clock signal

• US 5,247,656 A
• Filed: 05/23/1990
• Issued: 09/21/1993
• Est. Priority Date: 06/01/1989
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Taniguchi, Takashi, Kabuo, Hideyuki, Edamatsu, Hisakazu
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): SMITH, DIANE
• Application Number:
  US07/527,186
• Time in Patent Office: 1,217 Days
• Field of Search: 395/550, 364/270.2, 364/270.3, 364/271.2
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

A data processing device includes first and second blocks which have different processing times and which operate in synchronism with a clock signal. One of the first and second blocks is selected and enabled in accordance with an instruction representing which of the first and second blocks should be selected and enabled. A clock change signal is generated on the basis of the instruction. A period of the clock signal is changed in accordance with the clock change signal.

Claims

1. In a data processing circuit including first and second blocks which have different processing times and which operate in synchronism with a clock signal, wherein at least one of the first and second blocks is selected and enabled in accordance with an instruction changeable among first, second, and third states, the first state representing that the first block should be selected and enabled, the second state representing that the second block should be selected and enabled, the third state representing that both the first and second blocks should be selected and enabled, a method of controlling the clock signal, comprising the steps of:

detecting a current state of the instruction;

setting a period of the clock signal to a first predetermined period when the current state of the instruction is detected to be the first state;

setting the period of the clock signal to a second predetermined period when the current state of the instruction is detected to be the second state, the second predetermined period being longer than the first predetermined period; and

setting the period of the clock signal to the second predetermined period when the current state of the instruction is detected to be the third state.

2. The method of claim 1, wherein the second predetermined period is equal to twice the first predetermined period.

3. In a data processing circuit including first and second blocks which have different processing times and which operate in synchronism with a clock signal, wherein at least one of the first and second blocks is selected and enabled in accordance with first coded information of an instruction, the first coded information being changeable among first, second, and third states, the first state representing that the first block should be selected and enabled, the second state representing that the second block should be selected and enabled, the third state representing that both the first and second blocks should be selected and enabled, and wherein second coded information of the instruction represents a desired period of the clock signal, the desired period having a predetermined relation with which of the first and second blocks should be selected, a method of controlling the clock signal, comprising the steps of:

detecting a current state of the first coded information;

setting an actual period of the clock signal to a first predetermined period in response to the second coded information when the current state of the first coded information is detected to be the first state;

setting the actual period of the clock signal to a second predetermined period in response to the second coded information when the current state of the first coded information is detected to be the second state, the second predetermined period being longer than the first predetermined period; and

setting the actual period of the clock signal to the second predetermined period in response to the second coded information when the current state of the first coded information is detected to be the third state.

4. The method of claim 3, wherein the second predetermined period is equal to twice the first predetermined period.

5. In a data processing circuit including first and second blocks which have different processing times and which operate in synchronism with a clock signal, wherein at least one of the first and second blocks is selected and enabled in accordance with an instruction changeable among first, second, and third states, the first state representing that the first block should be selected and enabled, the second state representing that the second block should be selected and enabled, the third state representing that both the first and second blocks should be selected and enabled, an apparatus for controlling the clock signal, comprising:

means for detecting a current state of the instruction;

means for setting a period of the clock signal to a first predetermined period when the current state of the instruction is detected by the detecting means to be the first state;

means for setting the period of the clock signal to a second predetermined period when the current state of the instruction is detected by the detecting means to be the second state, the second predetermined period being longer than the first predetermined period; and

means for setting the period of the clock signal to the second predetermined period when the current state of the instruction is detected by the detecting means to be the third state.

6. The apparatus of claim 5, wherein the second predetermined period is equal to twice the first predetermined period.

7. In a data processing circuit including first and second blocks which have different processing times and which operate in synchronism with a clock signal, wherein at least one of the first and second blocks is selected and enabled in accordance with first coded information of an instruction, the first coded information being changeable among first, second, and third states, the first state representing that the first block should be selected and enabled, the second state representing that the second block should be selected and enabled, the third state representing that both the first and second blocks should be selected and enabled, and wherein second coded information of the instruction represents a desired period of the clock signal, the desired period having a predetermined relation with which of the first and second blocks should be selected, an apparatus for controlling the clock signal, comprising:

means for detecting a current state of the first coded information;

means for setting an actual period of the clock signal to a first predetermined period in response to the second coded information when the current state of the first coded information is detected by the detecting means to be the first state;

means for setting the actual period of the clock signal to a second predetermined period in response to the second coded information when the current state of the first coded information is detected by the detecting means to be the second state, the second predetermined period being longer than the first predetermined period; and

means for setting the actual period of the clock signal to the second predetermined period in response to the second coded information when the current state of the first coded information is detected by the detecting means to be the third state.

8. The apparatus of claim 7, wherein the second predetermined period is equal to twice the first predetermined period.

9. A data processing device comprising:

means for generating a clock signal having a period changeable between first and second predetermined periods, the second predetermined period being longer than the first predetermined period;

first and second data processing blocks which have different processing times and which operate in synchronism with the clock signal;

means for selecting and enabling at least one of the first and second blocks;

means for setting the period of the clock signal to the first predetermined period when the selecting/enabling means selects and enables the first block;

means for setting the period of the clock signal to the second predetermined period when the selecting/enabling means selects and enables the second block; and

means for setting the period of the clock signal to the second predetermined period when the selecting/enabling means selects and enables both the first and second blocks.

10. The apparatus of claim 9, wherein the second predetermined period is equal to twice the first predetermined period.

11. The apparatus of claim 9, wherein said means for selecting and enabling at least one of the first and second blocks comprises instruction decoding means responsive to an external instruction signal inputted to the data processing device.

12. The apparatus of claim 9, further comprising instruction decoding means responsive to an external instruction signal inputted to the data processing device, wherein said instruction decoding means comprises means for outputting a signal in accordance with coded information of the external instruction signal to effect setting of the clock period to the first and second predetermined periods.

13. The apparatus of claim 12, further comprising clock change signal generating means responsive to said signal outputted by said instruction decoding means for generating a clock change signal, said means for generating a clock signal being connected to receive said clock change signal.