Serial data transmission including idle bits

• US 5,247,657 A
• Filed: 09/14/1990
• Issued: 09/21/1993
• Est. Priority Date: 09/19/1989
• Status: Expired due to Fees

• Current Assignee: Psion PLC (Motorola Solutions, Inc.)
• Original Assignee: Psion PLC (Motorola Solutions, Inc.)
• Inventors: Myers, Nicholas S.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): GLEMBOCKI, CHRISTOPHE
• Application Number:
  US07/582,492
• Time in Patent Office: 1,103 Days
• Field of Search: 364/271.1, 364/271.2, 364/271.3, 364/271.4, 364/200, 395/550, 395/200, 395/800
• US Class Current: 709/236
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A serial data interface communicates data between a control processor (1) and one or more slave processors (2) via a serial bus (3). Typically the control processor (1) may be formed in a hand held or lap top computer and the slave processor (2) in a peripheral device for the computer. The control processor (1) transmits a clock signal over a clock line in the serial bus (3) to the slave processor (2). At the same time, control or data frames are transmitted from the control processor (1) the slave processor (2) or data frames are transmitted from the slave processor (3) to the control processor (1). Each data frame has a control portion which identifies the frame as a control frame or as a data frame, and following the control portion a plurality of data bits bounded by idle bits. Both the slave processor (2) and the control processor (1) free the data line for a change in the direction of data transmission during each idle bit.

In a preferred example, each control frame includes a select bit identifying the control frame as a slave select frame or as a slave control frame. Each slave control frame includes data transmission parameters which set the slave processor (2) to read or write one or more data frames subsequent to the current control frame.

Claims

1. A method of communicating data between first means for processing configured for a control function and second means for processing configured for a slave function over a serial interface;

wherein said interface comprises two lines only, a bi-directional data line and a uni-directional clock line;

said method comprising;

transmitting a clock signal from said first means for processing over said clock line to said second means for processing, and concurrently carrying out one of the two following functions;

(1) transmitting one of a control frame and data frame from said first means for processing over said serial interface to said second means for processing; and

(2) transmitting a data frame from said second means for processing over said serial interface to said first means for processing;

said method further comprising transmitting as part of each frame a control identification portion for identifying a frame as one of a control frame and a data frame, and transmitting following said control identification potion a plurality of data bits bounded by idle bits, both said first means for processing and said second means for processing freeing said bi-directional data line for a change in direction of data transmission during each said idle bit.

2. The method of claim 1, further comprising transmitting as one of said data bits of said control frame a select bit for identifying said control frame as one of a slave select frame and a slave control frame;

each slave select frame including as a further one of said data bits a reset bit, when said reset bit takes one predetermined value transmission of said slave select frame to said second means for processing causing said second means for processing to reset to a predetermined state, otherwise said transmission of said slave select frame to said second means for processing effecting one of selection and de-selection of said second means for processing;

each slave control frame including as one of said data bits data transmission parameters for setting said second means for processing to carry out one of reading and writing at least one data frame subsequent to a current control frame.

3. The method of claim 2, further comprising transmitting as one of said transmission parameters of said slave control frame a read/write bit for determining which one of reading and writing is carried out by said second means for processing in a subsequent data frame and a single unit/multiple unit flag bit for determining which of single and multiple units of data are communicated in said subsequent data frame.

4. The method of claim 3, further comprising assigning to said second means for processing a unique identification number and transmitting as one of said data bits of said slave select frame an identification field, said second means for processing in response to any slave select frame including as said identification field said unique identification number subsequently transmitting to said first means for processing a data frame including a predetermined information field.

5. The method of claim 4, wherein said first means for processing includes a variable rate clock, and means for generating a rate control signal for said variable rate clock and said means for generating output a modified rate control signal thereby adjusting a clock rate of said clock signal to a maximum rate compatible with said second means for processing in response to data in said predetermined information field.

6. A system for communicating serial data comprising:

first means for processing configured for a control function;

second means for processing configured for a slave function; and

serial interface means linking said first means for processing to said second means for processing, said serial interface means comprising a bi-directional data line and a uni-directional clock line only;

said first means for processing including means for generating a clock signal for transmission over said clock line to said second means for processing and concurrently carrying out one of the two following functions;

(1) transmitting one of a control frame and a data frame from said first means for processing over said serial interface means to said second means for processing; and

(2) receiving a data frame transmitted over said serial interface means form said second means for processing;

said first means for processing including first means for transmitting control frames and data frames onto said serial interface means and first means for reading data frames from said serial interface means;

and said second means for processing including second means for transmitting data frames onto said serial interface means, and second means for reading control frames and data frames from said serial interface means, and means for receiving said clock signal form said clock line and synchronizing said second means for transmitting and second means for reading with said first means for processing in response to said clock signal,

wherein said first and second means for transmitting and said first and second means for reading include means for transmitting and reading respectively frames comprising a control identification portion identifying a frame as one of a control frame and a data frame, and following said control portion a plurality of data bits bounded by idle bits, both said first and second means for processing freeing said data line for a change in direction of data transmission during each idle bit.

7. The system of claim 6, wherein each control frame includes as one of said data bits s select bit for identifying said control frame as one of a slave select frame and a slave control frame;

each slave select frame including as a further one of said data bits a reset bit, and said second means for processing including means for resetting said second means for processing to a predetermined state when said reset bit takes one predetermined value, and otherwise effecting one of selection and deselection in response to reading of said slave select frame by said second means for reading;

each slave control frame including as one of said data bits transmission parameters for setting said second means for processing to carry out one of reading and writing at least one data frame subsequent to a current control frame.

8. The system of claim 7, wherein said transmission parameters for said slave control frame include a read/write bit, said second means for processing including means responsive to said read/write bit for controlling said second reading means and second writing means to carry out one of reading or writing data in a succeeding data frame in accordance with a value of said read/write bit;

and

a single/multi bit, said second means for processing including means responsive to said single/multi bit for controlling said second reading means and second writing means to carry out one of reading and writing data in one of single and multiple units in subsequent data frames according to the value of said single/multi bit.

9. The system of claim 8, wherein said data bits of said slave select frame include an identification field, said second means for processing including means for storing a unique identification number and means responsive to any slave select frame including as its identification field said unique identification number subsequently to transmit to said first means for processing a data frame including a pre-determined information field.

10. The system of claim 9, wherein said first means for processing includes means responsive to said pre-determined information field for controlling said means for generating a clock signal to adjust a rate of said clock signal to a maximum rate compatible with said second means for processing.

11. Processor means configured for a control function and adapted for use in the system of claim 6.

12. A hand held computer including the processor means of claim 11.

13. A lap top computer including the processor means of claim 11.

14. Processor means configured for a slave function and adapted for use in the system claim 6.

15. A peripheral for a hand held computer including the processor means of claim 14.

16. The peripheral of claim 15, wherein said peripheral includes a mass storage device.

17. The peripheral of claim 16, wherein said mass storage device includes an FE² PROM.

18. A peripheral for a lap top computer including the processor means of claim 14.

19. The peripheral of claim 18, wherein said peripheral includes a mass storage device.

20. The peripheral of claim 19, wherein said mass storage device includes an FE² PROM.

21. A computing system comprising:

a portable personal computer including first means for processing configured for a control function;

a peripheral device including second means for processing configured for a slave function; and

serial interface means linking said first means for processing to said second means for processing for communication of serial data therebetween, said serial interface means comprising a bi-directional data line and a uni-directional clock line only;

generating a clock signal for transmission over said clock line to said second means for processing and concurrently carrying out one of the two following functions;

(1) transmitting one of a control frame and a data frame from said first means for processing over said serial interface means to said second means for processing; and

(2) receiving a data frame transmitted over said serial interface means from said second means for processing;

said first means for processing including first means for transmitting control frames and data frames onto said serial interface means and first means for reading data frames from said serial interface means;

and said second means for processing including second means for transmitting data frames onto said serial interface means and second means for reading control frames and data frames from said serial interface means,

wherein said first and second means for transmitting and said first and second means for reading include means for transmitting and reading respectively frames comprising a control portion identifying a frame as one of a control frame and a data frame, and following said control portion a plurality of data bits bounded by idle bits, both said first and second means for processing freeing said data line for a change in direction of data transmission during each idle bit, said second means for processing including means for receiving said clock signal from said clock line and synchronizing said second means for transmitting and second means for reading with said first means for processing in response to said clock signal.

22. The system of claim 21 wherein said peripheral device includes a mass storage device.

23. The system of claim 22 wherein said mass storage device includes an FE² PROM, said peripheral device including means electrically connected between said serial interface means and said FE² PROM for applying an erase voltage to said FE² PROM in response to a control signal from said second means for processing.