Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone

• US 5,248,893 A
• Filed: 01/05/1993
• Issued: 09/28/1993
• Est. Priority Date: 02/26/1990
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sakamoto, Shinichi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/000,593
• Time in Patent Office: 266 Days
• Field of Search: 357/23.1, 357/23.11, 357/55, 257/288, 257/409
• US Class Current: 257/409
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

An apparatus and method for forming an insulated gate field effect device including a first conductivity-type semiconductor substrate having a concave with a curved surface formed on the main surface, an insulating film formed on the major surface including the concave, a first and second impurity regions of a second conductivity-type formed in the vicinity of the main surface at one side and the other side of the concave, respectively, and a conductive layer formed on the channel region which is formed along the concave between the first and second impurity regions with the insulating film interposed therebetween. The method includes forming a concave with the curve surface on the main surface of a semiconductor substrate; forming an insulating film on the main surface, forming a conductive layer above the concave with an insulating film interposed therebetween; forming a first and second impurity regions of a second conductivity type in the vicinity of the main surface at one side and the other side of the concave.

Claims

1. An insulated gate field effect device comprising:

a first conductivity type semiconductor substrate having a main surface;

said semiconductor substrate having a concave surface formed on said main surface extending to a prespecified depth below the main surface;

an insulating film formed on said concave surface;

a conductive gate electrode formed above said insulating film, overlying the concave surface;

first and second impurity regions of a second conductivity type respectively formed in the substrate, in the vicinity of said main surfaces, self-aligned to and positioned at one side and the other side of said gate electrode respectively; and

a first conductivity type region located in said semiconductor substrate between said first and second impurity regions for defining a channel region and a channel-free region extending conformably under and along said concave surface;

wherein the depth of said concave surface is set to a value which ranges between one and two times the depth of said first and second impurity regions, and

wherein the concave surface is continuously curved in the vicinity of at least one of the first and second impurity regions to produce smooth merger of a conforming first depletion region formed around the at least one impurity region and a conforming second depletion region formed in the vicinity of the gate electrode so that excessive field concentration will not develop in the vicinity where the first and second depletion regions meet.

2. An insulated gate field effect device according to claim 1, wherein one of said first and second impurity regions constitutes a drain region of said insulated gate field effect device, the other of said first and second impurity regions constitutes a source region and wherein the concave surface is continuously curved at least in the vicinity of the drain region, where the channel-free region develops during an off state of the device, to produce smooth merger of the conforming first depletion region which develops in the vicinity of the channel-free region and the drain region and the conforming second depletion region formed in the vicinity of the gate electrode so that excessive field concentration will not develop in the vicinity of the channel-free region.

3. An insulated gate field effect device according to claim 1, which comprises a metal oxide semiconductor (MOS) transistor, and wherein said insulating film comprises an oxide film.

4. An insulated-gate field effect transistor comprising:

a substrate having a substantially planar main surface and a concave surface portion extending continuously from the main surface to a predetermined depth below the main surface;

an insulating layer conformably disposed on the main surface and the concave surface portion;

a gate conformably disposed on the insulating layer, overlying the concave surface portion, the gate having opposed first and second sides;

implanted source and drain regions disposed within the substrate and self-aligned to the respective first and second opposed sides of the gate; and

a channel-region formed between the source and drain regions, for defining a channel that conducts current between the source and drain regions when the transistor is in a turned-on state;

wherein a channel-free zone develops in the substrate, under the gate and between the source and drain regions, when the transistor is in a turned-off state; and

wherein the gate and concave surface portion are curved at least in the vicinity of the channel-free zone such that a smoothly curved depletion zone boundary will develop in the vicinity of the channel-free zone when the transistor is in the turned-off state.

5. An insulated-gate field effect transistor according to claim 4 wherein the concave surface portion is curved in a transverse cross-sectional plane extending through the transistor between but not intersecting the first and second sides of the gate so as to provide an effective channel width greater than a width of the channel as projected onto the plane of the main substrate surface.

6. An insulated-gate field effect transistor according to claim 5 wherein the concave surface portion is curved both in the transverse cross-sectional plane and in a non-transverse cross-sectional plane, extending between and joining the first and second sides of the gate, so as to provide an effective channel surface area greater than an area of the channel as projected onto the plane of the main substrate surface.

7. An insulated-gate field effect transistor according to claim 6 wherein the concave surface portion is equally curved both in the transverse cross-sectional plane and in the non-transverse cross-sectional plane, so as to provide a sheet-like depletion region having a uniform thickness and a smooth bottom boundary underlying the channel region and the source and drain regions, when the transistor is in a turned-off state.

8. An insulated-gate field effect transistor according to claim 4 wherein the concave surface portion is continuously curved from the point where it descends below and away from the main surface of the substrate to the point where it ascends to re-join the main surface of the substrate.

9. An insulated-gate field effect transistor according to claim 4 wherein the gate fills the void created by the concave surface portion and insulating layer at least from the level where the concave surface portion and insulating layer descend below the level of the main surface of the substrate.

10. An insulated-gate field effect transistor according to claim 4 wherein the concave surface portion is defined by isotropic plasma etching.

11. An insulated-gate field effect transistor according to claim 4 wherein the depth of the concave surface portion is set to a value which ranges between one and two times the depth of the source and drain regions.

12. An insulated-gate field effect transistor according to claim 4 wherein the depth of the drain region is 0.5 to 0.6 microns and the depth of the concave surface portion is set to approximately one micron.

13. An insulated-gate field effect transistor according to claim 4 wherein the concave surface portion is defined by focal ion beam etching.

14. An insulated-gate field effect transistor comprising:

a substrate having a substantially planar main surface and a concave surface portion extending continuously from the main surface to a predetermined depth below the main surface;

an insulating layer conformably disposed on the main surface and the concave surface portion;

a gate conformably disposed on the insulating layer, overlying the concave surface portion, the gate having opposed first and second sides;

implanted source and drain regions disposed within the substrate respectively at the first and second opposed sides of the gate, the drain region having a bottom surface which curves upwardly toward the top surface of the substrate; and

a channel-region formed between the source and drain regions, for defining a channel that conducts current between the source and drain regions when the transistor is in a turned-on state;

wherein a channel-free zone develops in the substrate, under the gate and between the source region and the upwardly curved bottom surface of the drain region, when the transistor is in a turned-off state; and

wherein the gate and concave surface portion are curved at least in the vicinity of the channel-free zone, and the upwardly curved bottom surface of the drain region is also curved, such that a smoothly curved depletion zone boundary will develop in the vicinity of the channel-free zone when the transistor is in the turned-off state.