Method for the hierarchical comparison of schematics and layouts of electronic components

• US 5,249,133 A
• Filed: 04/10/1991
• Issued: 09/28/1993
• Est. Priority Date: 04/10/1991
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Batra, Pradeep
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/684,047
• Time in Patent Office: 902 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578
• US Class Current: 716/112
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention takes advantage of the hierarchical nature of the design to perform a hierarchical comparison on as many blocks and sub-blocks which can be matched between the layout and the logic design. Because the internal connections were previously verified when the first occurrence of the block was compared, repetition of lengthy comparisons of multiple occurrences of the same blocks in the designs is avoided and subsequent comparisons are performed simply by comparing the input and output connections to the block.

Claims

1. A method for verifying a hierarchical circuit design, said circuit design comprising a schematic design, said schematic design comprising a net list specifying the logic devices of he circuit and the interconnection of the logic devices, and a layout design, said layout design comprising a net list specifying the physical layout and interconnection of devices, said schematic and layout designs being specified in hierarchical order wherein devices in each design are organized into blocks and blocks of a higher hierarchical order comprises blocks of a lower hierarchical order an devices, each block identified by a block name, said method comprising the steps of:

receiving the schematic net list and layout net list;

sorting separately the schematic net list and layout net list in hierarchical order;

comparing the schematic net list and layout net list to determine the blocks which occur in both the schematic net list and layout net list and;

marking those blocks which do not occur in both the schematic net list and layout net list;

generating a block list of unmarked blocks in hierarchical order which occur in both the schematic net list and layout net list;

comparing each unmarked block from the block list from the lowest hierarchical order to the highest hierarchical order comprising the steps of;

comparing a first instantiation of an unmarked lower hierarchical order block instantiated int he block to be compared by flattening the block to block components and comparing each instantiation of a block component in the schematic to determine if a corresponding block component at the same location connecting to the same nodes exists in the layout design, said instantiation verified if each instantiation of a block component in the schematic corresponds to a component in the layout design at the same location connecting to the same nodes,

adding the first instantiation of an unmarked lower hierarchical level block to a correspondence list, said correspondence list comprising a list of blocks by name and nodes into and out of each block, each of said nodes comprising an entry pair, a first element of the entry pair identifying the entry portion in the schematic for then done and a second element identifying the corresponding entry point in the layout,

comparing subsequent instantiations of verified unmarked lower hierarchical level blocks instantiated in the block by referencing the correspondence list to determine if the entry points in the schematic and layout of the instantiated block for each node of the block correspond, whereby if the entry points of the instantiated lower hierarchical block correspond as specified in the correspondence list, the instantiation of the block is verified, and

comparing instantiations of devices and marked lower hierarchical blocks by flattening each instantiation of each marked lower hierarchical block to devices and comparing each instantiation of a device in the schematic to determine if a corresponding device at the same location connecting to the same nodes exists in the layout design whereby the instantiation of the device is verified, and

reporting an error report of non-corresponding devices and instantiations of lower hierarchical level blocks;

whereby a design is verified in the minimal amount of time with a decrease in computational overhead because once a block is verified and added to the correspondence list, all subsequent instantiations of the same block are verified simply by verifying the correspondence of entry points at the nodes as specified in the correspondence list.

2. The method for verifying a hierarchical circuit design as set forth in claim 1, wherein the step of comparing a first instantiation of an unmarked block compares the block from the schematic to the block from layout using a graph isomorphism technique.

3. The method for verifying a hierarchical circuit design as set forth in claim 1, wherein each block is further identified by hierarchical identifier which identifies the hierarchical level the block belongs to and the step of generating a list of block names in hierarchical order comprises sorting the blocks according to the hierarchical identifier.

4. The method for verifying a hierarchical circuit design as set forth in claim 1, wherein the step of generating a list of block names in hierarchical order comprises determining the location of each block in the hierarchy in accordance with the blocks contained within the block and sorting the blocks in hierarchical order.

5. The method for verifying a hierarchical circuit design as set forth in claim 1, wherein the step of comparing a first instantiation of an unmarked hierarchical block further comprises comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.

6. The method for verifying a hierarchical circuit design as set forth in claim 1, wherein the step of comparing subsequent instantiations of an unmarked hierarchical block further comprises comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.

7. The method for verifying a hierarchical circuit design as set forth in claim 1, wherein each block is identified by a block name and the step of comparing the schematic net list and layout net list to initially determine the blocks which occur in both the schematic net list and layout net list comprises comparing the names of the blocks.

8. The method for verifying a hierarchical circuit design as set forth in claim 1, wherein block components comprise:

devices determined from flattening each unverified instantiation of an unmarked lower hierarchical level block and each marked block to the device level; and

subsequent instantiations of verified lower hierarchical level blocks.

9. A method for verifying a hierarchical circuit design, said circuit design comprising a schematic design, said schematic design comprising a net list specifying the logic devices of the circuit and the interconnection of the logic devices, and a layout design, said layout design comprising a net list specifying the physical layout and interconnection of devices, said schematic and layout designs being specified in hierarchical order wherein devices in each design are organized into blocks and blocks of a higher hierarchical order comprises blocks of a lower hierarchical order and devices, each block identified by a block name, said method comprising the steps of:

receiving the schematic net list and layout net list;

sorting separately the schematic net list and layout net list in hierarchical order;

comparing the schematic net list and layout net list to determine the block names which occur in both the schematic net list and layout net list and;

marking those blocks which do not occur in both the schematic net list and layout net list;

generating a block list of names of unmarked blocks in hierarchical order which occur in both the schematic net list and layout net list;

comparing each unmarked block from the block list from the lowest hierarchical order to the highest hierarchical order by comparing components and connections between blocks of the same name in the schematic net list and layout net list, said comprising the steps of;

comparing a first instantiation of an unmarked lower hierarchical level block instantiated in the block to be compared by flattening the block to the device level and comparing each instantiation of a device in the schematic to determine if a corresponding device at the same location connecting to the same nodes exists in the layout design,

adding the first instantiation of an unmarked lower hierarchical level block to a correspondence list, said correspondence list comprising a list of block names and nodes into and out of each block, each of said nodes comprising an entry pair, a first element of the entry pair identifying the entry point in the schematic for the node and a second element identifying the corresponding entry point in the layout,

comparing subsequent instantiations of unmarked lower hierarchical level blocks instantiated in the block by referencing the correspondence list to determine if the entry points in the schematic and layout of the instantiated block for each node of the block correspond, whereby if the entry points of the instantiated lower hierarchical block correspond as specified in the correspondence list, the instantiation of the block is verified, and

comparing instantiations of devices and marked lower hierarchical blocks by flattening each instantiation of each marked lower hierarchical block to devices and comparing each instantiation of a device in the schematic to determine if a corresponding device at the same location connecting to the same nodes exists in the layout design whereby the instantiation of the device is verified, and

reporting an error report of non-corresponding devices and instantiations lower hierarchical level blocks;

whereby a design is verified in the minimal amount of time with a decrease in computational overhead because once a block is verified and added to the correspondence list, all subsequent instantiations of the same block are verified simply by verifying the correspondence of entry points at the nodes as specified in the correspondence list.

10. The method for verifying a hierarchical circuit design as set forth in claim 9, wherein the step of comparing a first instantiation of an unmarked block compares the block from the schematic to the block from layout using a graph isomorphism technique.

11. The method for verifying a hierarchical circuit design as set forth in claim 9, wherein the step of comparing a first instantiation of an unmarked hierarchical block further comprises comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.

12. The method for verifying a hierarchical circuit design as set forth in claim 9, wherein the step of comparing subsequent instantiations of an unmarked hierarchical block further comprises comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.

13. A test apparatus for verifying a hierarchical circuit design, said circuit design comprising a schematic design, and schematic design comprising a net list specifying the logic devices of the circuit and the interconnection of the logic devices, and a layout design, said layout design comprising a net list specifying the physical layout and interconnection of devices, said schematic and layout designs being specified in hierarchical order wherein devices in each design are organized into blocks and blocks of a higher hierarchical order comprises blocks of a lower hierarchical order and devices, each block identified by a block name, said testing apparatus comprising a central processing unit (CPU) memory, and input/out means, said apparatus further comprising:

input means for receiving the schematic net list and layout net list;

sorting means for separately sorting the schematic net list and layout net list in hierarchical order;

a first comparison means for comparing the schematic net list and layout net list to determine the block names which occur in both the schematic net list and layout net list and marking those blocks which do not occur in both the schematic net list and layout net list;

extraction means for generating a block list of names of unmarked blocks in hierarchical order which occur in both the schematic net list and layout net list;

a correspondence list comprising a list of unmarked block names and nodes into and out of the block, each of said nodes comprising an entry pair, a first element of the entry pair identifying the entry point in the schematic for the node and a second element identifying the corresponding entry point in the layout, a bock name being included in the correspondence list if the components and connections of a block in the schematic net list match the components and connections of a block of the same name in the layout net list;

a second comparison means for comparing unmarked blocks from the lowest hierarchical order to the highest hierarchical order, said comparison means comparing components and connections between unmarked blocks of the same name in the schematic net list and layout net list, said second comparison means comprising;

means for comparing a first instantiation of an unmarked lower hierarchical level block to verify the block by flattening the block to block components and comparing each instantiation of a block component in the schematic design to determine if a corresponding component at the same location connecting to the same nodes exists in the layout design, and verifying the instantiation of the block and adding the instantiation to the correspondence list if each block component in the schematic corresponds to a block component in the layout,

means for comparing subsequent instantiations of unmarked lower hierarchical level blocks by referencing the correspondence list to determine if the entry points in the schematic design and layout design of the instantiated block for each node of the block correspond, whereby if the entry points of the instantiated lower hierarchical block correspond as specified in the correspondence list, the instantiation of the block is verified, and

means for comparing instantiations of devices and marked lower hierarchical blocks by flattening each instantiation of each marked lower hierarchical block to devices and comparing each instantiation of a device in the schematic design to determine if a corresponding device at the same location connecting to the same nodes exists in the layout design whereby the instantiation of the device is verified, and

reporting means for generating an error report of non-corresponding devices and instantiations lower hierarchical level blocks;

whereby a design is verified in the minimal amount of time with a decrease in computational overhead because once a block is verified and added to the correspondence list, all subsequent instantiations of the same block are verified simply by verifying the correspondence of entry points at the nodes as specified in the correspondence list.

14. The test apparatus for verifying a hierarchical circuit design as set forth in claim 13, wherein the means for comparing a first instantiation of an unmarked block comprises a graph isomorphism comparison mechanism.

15. The test apparatus for verifying a hierarchical circuit design as set forth in claim 13, wherein the means for comparing a first instantiation of an unmarked hierarchical block further comprises a means for comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.

16. The test apparatus for verifying a hierarchical circuit design as set forth in claim 13, wherein the means for comparing subsequent instantiations of an unmarked hierarchical block further comprises means for comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.

17. The test apparatus for verifying a hierarchical circuit design as set forth in claim 13, wherein block components comprise:

devices determined from flattening each unverified instantiation of an unmarked lower hierarchical level block and each marked block to the device level; and

subsequent instantiations of verified lower hierarchical level blocks.

18. A test apparatus for verifying a hierarchical circuit design, said circuit design comprising a schematic design, said schematic design comprising at net list specifying the logic devices of the circuit and the interconnection of the logic devices, and a layout design, said layout design comprising a net list specifying the physical layout and interconnection of devices, said schematic and layout designs being specified in hierarchical order wherein devices in each design are organized into blocks and blocks of a higher hierarchical order comprises blocks of a lower hierarchical order and devices, each block identified by a block name, said testing apparatus comprising a central processing unit (CPU) memory, and input/out means, said apparatus further comprising:

input means for receiving the schematic net list and layout net list;

sorting means for separately sorting the schematic net list and layout net list in hierarchical order;

a first comparison means for comparing the schematic net list and layout list to determine the block names which occur in both the schematic net list and layout net list and marking those blocks which do not occur in both the schematic net list and layout net list;

extraction means for generating a block list of names of unmarked blocks in hierarchical order which occur in both the schematic net list and layout net list;

a correspondence list comprising a list of unmarked block names and nodes into an out of the block, each of said nodes comprising an entry pair, a first element of the entry pair identifying the entry point in the schematic for the node and a second element identifying the corresponding entry point in the layout, a block name being included in the correspondence list if the components and connections of a block in the schematic net list match the components and connections of a block of the same name in the layout net list

a second comparison means for comparing unmarked blocks form the lowest hierarchical order to the highest hierarchical order, said comparison means comparing components and connections between unmarked blocks of the same name in the schematic net list and layout net list, said second comparison means comprising;

means for comparing the first instantiation of an unmarked lower hierarchical level blocks to verify the block by flattening the block to the device level and comparing each instantiation of a device in the schematic design to determine if a corresponding device at the same location connecting to the same nodes exists in the layout design, whereby the instantiation of the device is verified and added to the correspondence list,

means for comparing subsequent instantiations of unmarked lower hierarchical level blocks by referencing the correspondence list to determine if the entry points in the schematic design and layout design of the instantiated block of reach node of the block correspond, whereby if the entry points of the instantiated lower hierarchical block correspond as specified in the correspondence list, the instantiation of the block is verified, and

means for comparing instantiations of devices and marked lower hierarchical blocks by flattening each instantiation of each marked lower hierarchical block to devices and comparing each instantiation of a device in the schematic design to determine if a corresponding device at the same location connecting to the same nodes exists in the layout design whereby the instantiation of the device is verified, and

reporting means for generating an error report of non-corresponding devices and instantiations lower hierarchical level blocks;

whereby a design is verified, in the minimal amount of time with a decrease in computational overhead because once a block is verified and added to the correspondence list, all subsequent instantiation of the same block are verified simply by verifying the correspondence of entry points at the nodes as specified in the correspondence list.

19. The test apparatus for verifying a hierarchical circuit design as set forth in claim 18, wherein the means for comparing a first instantiation of an unmarked block comprises a graph isomorphism comparison mechanism.

20. The test apparatus for verifying a hierarchical circuit design as set forth in claim 18, wherein the means for comparing a first instantiation of an unmarked hierarchical block further comprises a means for comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.

21. The test apparatus for verifying a hierarchical circuit design as set forth in claim 18, wherein the means for comparing subsequent instantiations of an unmarked hierarchical block further comprises means for comparing the size of the block in the schematic to the size of block in the layout to determine if the blocks are equal in size.