Method of layout processing including layout data verification

• US 5,249,134 A
• Filed: 12/18/1991
• Issued: 09/28/1993
• Est. Priority Date: 04/12/1988
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Oka, Akihisa
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/810,353
• Time in Patent Office: 650 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 371/23
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A method of processing layout data of an integrated circuit including several circuit blocks and inter-block routing among the circuit blocks on data verification. The method includes the steps of processing layout data within at least one of the circuit blocks and replacing the layout data within that circuit block with layout data in a peripheral neighborhood region of that circuit block to process the replaced layout data.

Claims

1. A computer implemented method requiring reduced data storage capacity for processing layout data of an integrated circuit, the circuit including a plurality of circuit blocks and inter-block routing among said plurality of circuit blocks, comprising the steps of:

using a computer to perform a design rule check for layout data for at least one but not all of said plurality of circuit blocks;

using a computer to replace the layout data for said at least one circuit block by replacement internal routing layout data for a peripheral neighborhood region of said at least one circuit block; and

using a computer to process said inter-block routing and said replacement internal routing layout data by performing said design rule check thereon,

whereby a smaller amount of memory is required in the computer than required for performing the design rule check for layout data for all of said plurality of circuit blocks.

2. A computer implemented method of processing layout data as claimed in claim 1, wherein said step of using a computer to process said inter-block routing and said replacement internal routing layout data comprises using the computer to perform a layout design rule check for said inter-block routing data and for said replacement internal routing layout data, thereby reducing an amount of memory required for the layout design rule check for the integrated circuit.

3. A computer implemented method of processing layout data as claimed in claim 1, comprising the further step of performing a frame-cut operation after said step of using the computer to perform a design rule check for the layout data of said at least one of said plurality of circuit blocks, and

wherein said step of using the computer to replace the layout data for said at least one circuit block by replacement internal routing layout data for a peripheral neighborhood region comprises replacing the layout data for said at least one circuit block by frame data corresponding to the layout data in peripheral regions within a minimum line-width of a periphery of said at least one circuit block.

4. A computer implemented method of processing layout data as claimed in claim 3, wherein said step of using a computer to process said inter-block routing and said replacement internal routing layout data comprises using the computer to perform a layout design rule check for said inter-block routing data and for said replacement internal routing layout data, thereby reducing an amount of memory required for the layout design rule check for the integrated circuit.

5. A computer implemented method of processing layout data as claimed in claim 1, wherein said replacement internal routing layout data for the peripheral neighborhood region is data within a minimum line width from said inter-block routing.

6. A computer implemented method of processing layout data as claimed in claim 1, comprising the further steps of:

using a computer to perform a design rule check for layout data for another of said plurality of circuit blocks;

using a computer to replace the layout data for said another circuit block by replacement internal routing layout data for a peripheral neighborhood region of said another circuit block; and

using a computer to process said inter-block routing and said replacement internal routing layout data for said another circuit block.

7. A computer implemented method requiring reduced data storage capacity for processing layout data of an integrated circuit, the circuit including a plurality of circuit blocks and inter-block routing among said plurality of circuit blocks, comprising the steps of:

using a computer to perform a design rule check for layout data for said plurality of circuit blocks;

then

using a computer to replace the layout data for at least one of said plurality of circuit blocks by replacement internal routing layout data for only a peripheral neighborhood region of said at least one circuit block; and

using a computer to process said inter-block routing and said replacement internal routing layout data,

whereby a smaller amount of memory is required in the computer than required for performing the design rule check for layout data for all of said plurality of circuit blocks and said inter-block routing.

8. A computer implemented method of processing layout data as claimed in claim 7, wherein said step of using a computer to process said inter-block routing and said replacement internal routing layout data comprises using the computer to perform a layout design rule check for said inter-block routing data and for said replacement internal routing layout data, thereby reducing an amount of memory required for the layout design rule check for the integrated circuit.

9. A computer implemented method of processing layout data as claimed in claim 7, comprising the further step of performing a frame-cut operation after said step of using the computer to perform a design rule check for the layout data for said plurality of circuit blocks, and

wherein said step of using the computer to replace the layout data for said at least one circuit block by replacement internal routing layout data for a peripheral neighborhood region comprises replacing the layout data for said at least one circuit block by frame data corresponding to the layout data in peripheral neighborhood regions of said at least one circuit block.

10. A computer implemented method of processing layout data as claimed in claim 9, wherein said step of using a computer to process said inter-block routing and said replacement internal routing layout data comprises using the computer to perform a layout design rule check for said inter-block routing data and for said replacement internal routing layout data, thereby reducing an amount of memory required for the layout design rule check for the integrated circuit.

11. A computer implemented method of processing layout data as claimed in claim 7, wherein said replacement internal routing layout data for the peripheral neighborhood region is data within a minimum line width from said inter-block routing.

12. A computer implemented method of processing layout data as claimed in claim 7, comprising the further steps of:

using a computer to replace the layout data for another of said plurality of circuit blocks by replacement internal routing layout data for a peripheral neighborhood region of said another circuit block; and

using a computer to process said inter-block routing and said replacement internal routing layout data for said another circuit block.

13. A computer implemented method requiring reduced data storage capacity for layout design rule check of an integrated circuit, said circuit including a plurality of circuit blocks and inter-block routing among said plurality of circuit blocks, comprising the steps of:

using a computer to perform a layout design rule check for layout data for at least one but not all of said plurality of circuit blocks;

using a computer to replace the layout data for said at least one circuit block by replacement internal routing layout data for a peripheral neighborhood region of said at least one circuit block within a minimum line width from said inter-block routing; and

using a computer to perform the layout design rule check for said inter-block routing and said replacement internal routing layout data, thereby reducing an amount of memory required for performing the layout design rule check for all of said circuit blocks of the integrated circuit and the inter-block routing.

14. A computer implemented method of processing layout data as claimed in claim 13, comprising the further step of performing a frame-cut operation after said step of using the computer to perform a layout design rule check for the layout data for said at least one of said plurality of circuit blocks, and

wherein said step of using the computer to replace the layout data for said at least one circuit block by replacement internal routing layout data for a peripheral neighborhood region comprises replacing the layout data for said at least one circuit block by frame data corresponding to the layout data in peripheral neighborhood regions of said at least one circuit block.

15. A computer implemented method of processing layout data as claimed in claim 13, comprising the further steps of:

using a computer to perform a layout design rule check for layout data for another of said plurality of circuit blocks;

using a computer to replace the layout data for said another circuit block by replacement internal routing layout data for a peripheral neighborhood region of said another circuit block within a minimum line width of said inter-block routing from a periphery of said another circuit block; and

using a computer to perform a layout design rule check for said inter-block routing and said replacement internal routing layout data of said another circuit block.