Memory cell array divided type multi-port semiconductor memory device

• US 5,249,165 A
• Filed: 03/06/1992
• Issued: 09/28/1993
• Est. Priority Date: 03/07/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Toda, Haruki
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/846,913
• Time in Patent Office: 571 Days
• Field of Search: 365/189.01, 365/189.04, 365/230.05
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A memory cell array divided type multi-port memory device having random access circuit and serial access circuit, including: a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being disposed in a column direction at a predetermined pitch, each the cell array section having a plurality of word lines and bit lines, the word lines being connected to the memory cells disposed in a row direction for selection of the connected memory cells, and the bit lines being connected to the memory cells disposed in a column direction for data transfer to and from the selected memory cells; a row decoder for activating a desired one of the word lines; sense amplifier provided for each the bit line for sensing data read out to each the bit line; a RAM port connected to the bit lines via RAM transfer gates; a column decoder for selectively turn on/off the RAM transfer gates; a plurality of data transfer lines each having a data transfer gate at the intermediate position thereof, the data transfer lines being connected to the bit lines and formed on a layer different from layers of the word lines and bit lines; data transfer gate control means for turning on/off a desired one of the data transfer gates; a plurality of serial resisters connected to the data transfer lines; a serial port connected via each serial transfer gate to each the serial register; and a serial decoder for serially turning on/off the serial transfer gates.

Claims

1. A memory cell array divided type multi-port memory device having random access means and serial access means, comprising:

a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, said plurality of cell array sections being disposed in a column direction at a predetermined pitch, each said cell array section having a plurality of word lines and bit lines, said word lines being connected to said memory cells disposed in a row direction for selection of said connected memory cells, and said bit lines being connected to said memory cells disposed in a column direction for data transfer to and from said selected memory cells;

a row decoder for activating a desired one of said word lines;

sense amplifier means provided for each said bit line for sensing data read out to each said bit line;

a RAM port connected to said bit lines via RAM transfer gates;

a column decoder for selectively turn on/off said RAM transfer gates;

a plurality of data transfer lines each having a data transfer gate at the intermediate position thereof, said data transfer lines being connected to said bit lines and formed on a layer different from layers of said word lines and bit lines;

data transfer gate control means for turning on/off a desired one of said data transfer gates;

a plurality of serial resisters connected to said data transfer lines;

a serial port connected via each serial transfer gate to each said serial register; and

a serial decoder for serially turning on/off said serial transfer gates.

2. A multi-port memory device according to claim 1, wherein random access to said cell array sections is executed asynchronously with serial access.

3. A multi-port memory device according to claim 1, wherein the number of said cell array sections is at least three.

4. A multi-port memory device according to claim 3, wherein substantially two halves of said cell array sections are disposed respectively at the right and left sides of said serial registers and said serial decoder in a column direction.

5. A multi-port memory device according to claim 1, wherein said word lines, said bit lines, and said data transfer lines, are formed on three different layers, respectively.

6. A multi-port memory device according to claim 3, wherein said word lines, said bit lines, and said data transfer lines, are formed on three different layers, respectively.

7. A multi-port memory device according to claim 4, wherein said word lines, said bit lines, and said data transfer lines, are formed on three different layers, respectively.

8. A multi-port memory device according to claim 1, wherein said sense amplifier means is provided for each said cell array section.

9. A multi-port memory device according to claim 5, wherein said sense amplifier means is provided for each said cell array section.

10. A multi-port memory device according to claim 6, wherein said sense amplifier means is provided for each said cell array section.

11. A multi-port memory device according to claim 7, wherein said sense amplifier means is provided for each said cell array section.

12. A multi-port memory device according to claim 1, wherein said sense amplifier means is provided for each said cell array sections.

13. A multi-port memory device according to claim 9, wherein an initial sense portion of said sense amplifier means is provided for each said cell array section, and one restore portion of said sense amplifier means is provided in common for the plurality of said cell array sections.

14. A multi-port memory device according to claim 1, wherein said row decoder activates a desired one of said word lines in one of said cell array sections during one access cycle.

15. A multi-port memory device according to claim 8, wherein said row decoder activates a desired one of said word lines in one of said cell array sections during one access cycle.

16. A multi-port memory device according to claim 9, wherein said row decoder activates a desired one of said word lines in one of said cell array sections during one access cycle.

17. A multi-port memory device according to claim 10, wherein said row decoder activates a desired one of said word lines in one of said cell array sections during one access cycle.

18. A multi-port memory device according to claim 11, wherein said row decoder activates a desired one of said word lines in one of said cell array sections during one access cycle.

19. A multi-port memory device according to claim 1, wherein in a data transfer cycle between said selected memory cells and said serial registers, said data transfer gate control means turns on only said data transfer gates on said data transfer lines connecting said serial registers to said bit lines in said cell array section belonging to said selected memory cells.

20. A multi-port memory device according to claim 15, wherein in a data transfer cycle between said selected memory cells and said serial registers, said data transfer gate control means turns on only said data transfer gates on said data transfer lines connecting said serial registers to said bit lines in said cell array section belonging to said selected memory cells.

22. A multi-port memory device according to claim 17, wherein in a data transfer cycle between said selected memory cells and said serial registers, said data transfer gate control means turns on only said data transfer gates on said data transfer lines connecting said serial registers to said bit lines in said cell array section belonging to said selected memory cells.

23. A multi-port memory device according to claim 18, wherein in a data transfer cycle between said selected memory cells and said serial registers, said data transfer gate control means turns on only said data transfer gates on said data transfer lines connecting said serial registers to said bit lines in said cell array section belonging to said selected memory cells.

21. A multi-port memory device according to clam 16, wherein in a data transfer cycle between said selected memory cells and said serial registers, said data transfer gate control means turns on only said data transfer gates on said data transfer lines connecting said serial registers to said bit lines in said cell array section belonging to said selected memory cells.