Object reuse protection with error correction

• US 5,249,212 A
• Filed: 06/01/1992
• Issued: 09/28/1993
• Est. Priority Date: 06/01/1992
• Status: Expired due to Term

• Current Assignee: General Dynamics C4 Systems Incorporated (General Dynamics Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Covey, Carlin R., Gorowara, Hemant K.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/891,126
• Time in Patent Office: 484 Days
• Field of Search: 371/2.1, 371/2.2, 371/37.1, 371/37.2, 371/37.7, 371/49.1, 371/40.1, 371/40.2, 371/40.4
• US Class Current: 714/765
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 12/1458 by checking the subject access rights

Abstract

A method and apparatus for providing error detection, correction and prevention of unauthorized access to data using memory tags. The method and apparatus includes computing an original error detection/correction code associated with a data word. The original error detection/correction code, using a CPU and a subject identification register, is copied to a tag associated with the data word when an original subject writes the data word into a memory. A single-error-correction/double-error detection (SEC/DED) device applies a first bias to the tag to create a first-biased error detection/correction code when the memory is assigned to a first subject. The SEC/DED device applies a second bias to create a twice-biased error detection/correction code when a second subject attempts to access the data word. Access to the data word is denied if the twice-biased error detection/correction code comprises an uncorrectable error.

Claims

1. A method for combined error detection/correction and object reuse protection in a computer, the method comprising the steps of:

computing an original error detection/correction code associated with a data word;

applying a first forward bias to the original error detection/correction code to create a first forward-biased error detection/correction code when a first subject writes the data word into a memory location;

copying the first forward-biased error detection/correction code to a tag associated with the data word;

applying a first reverse-bias to the first forward-biased error detection/correction code when the memory location is read by the first subject;

permitting the first subject to read the data word with the first reverse-bias canceling the first forward-biased error detection/correction code;

applying a second reverse-bias to the first-biased error detection/correction code to create a still-biased error detection/correction code when a second subject attempts to access the data word; and

denying access to the data word if the still-biased error detection/correction code comprises an uncorrectable error.

2. A method for combined error detection/correction and object reuse protection as claimed in claim 1, wherein the step of denying access comprises the step of aborting a read operation.

3. A method for combined error detection/correction and object reuse protection as claimed in claim 1, wherein the step of applying a first forward-bias comprises the step of applying a first forward-bias to create a first forward-biased error detection/correction code based on a single-error-correction/double-error-detection (SEC/DED) Hamming code.

4. A method for combined error detection/correction and object reuse protection as claimed in claim 3, wherein the steps of applying a first reverse-bias and applying a second reverse-bias each comprise the step of applying a single-error-correction/double-error-detection (SEC/DED) Hamming code.

5. A method for combined error detection/correction and object reuse protection as claimed in claim 4, wherein the steps of applying a first forward-bias, applying a first reverse-bias, and applying a second reverse-bias each further comprise the step of computing an error syndrome for the data word.

6. A method for combined error detection/correction and object reuse protection as claimed in claim 5, wherein the step of computing an error syndrome comprises the steps of:

computing a new error code pattern from the data word; and

exclusive-ORing the new error code pattern from the data word with the tag.

7. In a computer, a device for providing combined error detection/correction and object reuse protection, the device comprising:

a central processing unit (CPU);

a memory means for storing a data word and a corresponding tag identifying a first process with a first identification (ID), the memory means coupled to the CPU;

a subject ID register for storing a current process ID for a current process, the subject ID register coupled to the CPU and the memory means; and

single-error-correction/double-error-detection (SEC/DED) means for determining errors in the data word, the SEC/DED means comprising;

a SEC/DED generator for generating an error code pattern, the SEC/DED generator coupled to the CPU; and

a bias adder for changing the error code pattern to a first forward-biased error code pattern based on the first ID when the data word is written into the memory, the bias adder coupled to the memory means, to the subject ID register, and to the SEC/DED generator.

8. In a computer, a device for providing combined error detection/correction and object reuse protection as claimed in claim 7, wherein the SEC/DED means further comprises a bias subtractor for subtracting a second reverse-bias from the first forward-biased error code pattern to create a still-biased error code pattern, the second reverse-bias based on a second subject identification (ID) from a second subject accessing the data word from the memory, the bias subtractor coupled to the memory means and to the subject ID register.

9. In a computer, a device for providing combined error detection/correction and object reuse protection as claimed in claim 8, wherein the SEC/DED means further comprises a SEC/DED checker for aborting the accessing if the twice-biased error code pattern is read as an uncorrectable error, the SEC/DED checker coupled to the CPU, to the SEC/DED generator, and to the bias subtractor.

10. A device for providing combined error detection/correction and object reuse protection, the device comprising:

a central processing unit (CPU);

a memory means for storing a data word and a corresponding tag identifying a first process with a first identification (ID), the memory means coupled to the CPU;

a subject ID register for storing a current process ID for a current process, the subject ID register coupled to the CPU and the memory means; and

single-error-correction/double-error-detection (SEC/DED) means for determining errors in the data word, the SEC/DED means comprising;

a SEC/DED generator for generating an error code pattern, the SEC/DED generator coupled to the CPU; and

a bias adder for changing the error code pattern to a first biased error code pattern based on the first ID when the data word is written into the memory, the bias adder coupled to the memory means, to the subject ID register, and to the SEC/DED generator.

11. A device for providing combined error detection/correction and object reuse protection as claimed in claim 10, wherein the SEC/DED means further comprises a bias subtractor for subtracting a second bias from the first biased error code pattern to create a twice-biased error code pattern, the second bias based on a second subject identification (ID) associated with a second subject accessing the data word from the memory, the bias subtractor coupled to the memory means and to the subject ID register.

12. A device for providing combined error detection/correction and object reuse protection as claimed in claim 11, wherein the SEC/DED means further comprises a SEC/DED checker for aborting the accessing if the twice-biased error code pattern is read as an uncorrectable error, the SEC/DED checker coupled to the CPU, to the SEC/DED generator, and to the bias subtractor.

13. A method for providing error detection/correction and prevention of unauthorized access to data using memory tags, the method comprising the steps of:

computing an original error detection/correction code associated with a data word;

applying a first bias to the original error detection/correction code to create a first-biased error detection/correction code when the memory is assigned to a first subject;

copying the first-biased error detection/correction code to a tag associated with the fata word when the first subject writes the data word into a memory location;

applying a second bias to the first-biased error detection/correction code to create a twice-biased error detection/correction code when a second subject attempts to access the data word; and

denying access to the data word if the twice-biased error detection/correction code comprises an uncorrectable error.

14. A method for providing error detection/correction and prevention of unauthorized access to data using memory tags as claimed in claim 13, wherein the step of denying access comprises the step of aborting a read operation.

15. A method for providing error detection/correction and prevention of unauthorized access to data using memory tags as claimed in claim 13, wherein the step of applying a first bias to the original error detection/correction code comprises the step of applying a first bias to the original error detection/correction code based on a single-error-correction/double-error-detection (SEC/DED) Hamming code.

16. A method for providing error detection/correction and prevention of unauthorized access to data using memory tags as claimed in claim 13, wherein the step of applying a second bias to the original error detection/correction code comprises the step of applying a second bias to the original error detection/correction code based on a single-error-correction/double-error-detection (SEC/DED) Hamming code.