Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

• US 5,250,450 A
• Filed: 02/12/1992
• Issued: 10/05/1993
• Est. Priority Date: 04/08/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando, Lee, Ruojia
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Pham, Long
• Application Number:
  US07/835,691
• Time in Patent Office: 601 Days
• Field of Search: 437/40, 437/43, 257/327
• US Class Current: 438/270
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical

Abstract

An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portions of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

Claims

1. A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of:

a) providing a semiconductor substrate of a first conductivity type having a reference surface;

b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface;

c) forming an insulated gate layer on the sidewall;

d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench;

e) partially filling the trench with a spacer dielectric layer, by;

depositing a spacer dielectric layer atop the surface of the trench;

planarizing the spacer dielectric layer on the mesa of the trench; and

etching the spacer dielectric layer in the base of the trench to a predetermined thickness;

f) forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer dielectric layer to the reference surface; and

g) the conductive layer being spaced apart from the second layer of the second conductivity type by the spacer dielectric layer to decrease a parasitic capacitance between the conductive layer and the second layer of the second conductivity type.

2. A method according to claim 1 including the step of sizing the thickness of the spacer dielectric layer to decrease the parasitic capacitance below a predetermined capacitance.

3. A method according to claim 2 in which the step of sizing the thickness of the spacer dielectric comprises etching the spacer dielectric to a predetermined thickness.

4. A method according to claim 1 in which the step of forming an insulated gate layer on the sidewall comprises the steps of:

forming a gate dielectric layer on the surface of the trench;

forming a gate conductive layer atop the gate dielectric layer; and

selectively removing the gate dielectric layer and the gate conductive layer from the mesa and the base of the trench.

5. A method according to claim 1 in which the step of forming the first layer of the second conductivity type in the mesa comprises forming the first layer of the second conductivity type in a first portion of the mesa.

6. A method according to claim 5 comprising the steps of:

extending the insulated gate layer above the reference surface and onto a second portion of the mesa; and

extending the conductive layer above the reference surface and onto the insulated gate layer on the second portion of the mesa.

7. A method according to claim 6 comprising the steps of:

forming a field dielectric layer covering the conductive layer on the second portion of the mesa;

opening the field dielectric layer covering the conductive layer on the second portion of the mesa to form a gate contact; and

covering the gate contact with an interconnect line.

8. A method according to claim 5 comprising the steps of:

forming a field dielectric layer covering first layer of the second conductivity type on the first portion of the mesa;

opening the field dielectric layer above the first layer of the second conductivity type on the first portion of the mesa to form a first current node contact; and

covering the first current node contact with an interconnect line.

9. A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of:

a) providing a semiconductor substrate of a first conductivity type having a reference surface;

b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface;

c) forming an insulated gate layer on the sidewall;

d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench;

e) forming a conductor that extends from the mesa of the trench to the base of the trench to ohmically contact the second layer of the second conductivity type;

f) partially filling the trench with a spacer dielectric layer; and

g) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench for ohmic contact with the conductor.

10. A method according to claim 9 in which the step of forming a conductor comprises forming a conductor that is electrically insulated from the insulated gate layer and from the first layer of the second conductivity type.

11. A method according to claim 9 in which the step of forming an insulated gate layer on the sidewall comprises the steps of:

forming a gate dielectric layer on the surface of the trench;

forming a gate conductive layer atop the gate dielectric layer; and

selectively removing the gate dielectric layer and the conductive layer from the mesa and the base of the trench.

12. A method according to claim 9 in which the step of partially filling the trench comprises the steps of:

depositing a spacer dielectric layer atop the surface of the trench;

planarizing the spacer dielectric layer on the mesa of the trench; and

etching the spacer dielectric layer in the base of the trench to a predetermined thickness.

13. A method according to claim 9 including the step of forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer oxide layer to the reference surface.

14. A method according to claim 9 comprising the steps of:

opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench;

forming a field dielectric layer covering the second layer the second conductivity type in the base of the trench;

opening the field dielectric layer above the second layer of the second conductivity type to form a second current node contact; and

ohmically contacting the second current node contact with the conductor.

15. A method according to claim 9 in which the step of forming the first layer of the second conductivity type in the mesa comprises forming the first layer of the second conductivity type in a first portion of the mesa.

16. A method according to claim 15 comprising the steps of:

extending the insulated gate layer above the reference surface and onto a second portion of the mesa; and

extending the conductive layer above the reference surface and onto the insulated gate layer on the second portion of the mesa.

17. A method according to claim 16 comprising the steps of:

forming a field dielectric layer covering the conductive layer on the second portion of the mesa;

opening the field dielectric layer above the conductive layer on the second portion of the mesa to form a gate contact; and

covering the gate contact with an interconnect line.

18. A method according to claim 15 comprising the steps of:

forming a field dielectric layer covering the first layer of the second conductivity type on the first portion of the mesa;

opening the field dielectric layer above the first layer of the second conductivity type on the first portion of the mesa to form a first current mode contact; and

covering the first current node contact with an interconnect line.

19. A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of:

a) providing a semiconductor substrate of a first condustivity type having a reference surface;

b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface;

c) forming an insulated gate layer on the sidewall;

d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench;

e) partially filling the trench with a spacer dielectric layer;

f) forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer dielectric layer to the reference surface;

g) the conductive layer being spaced apart from the second layer of the second conductivity type by the spacer dielectric layer to decrease a parasitic capacitance between the conductive layer and the second layer of the second conductivity type;

h) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench; and

i) forming a field dielectric layer covering the second layer of the second conductivity type in the base of the trench;

j) opening the field dielectric layer above the second layer of the second conductivity type to form a second current node contact; and

k) covering the second current node contact with an interconnect line.