Method for fabricating an optical semiconductor device

• US 5,250,462 A
• Filed: 08/26/1991
• Issued: 10/05/1993
• Est. Priority Date: 08/24/1990
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Katoh, Tomoaki, Sasaki, Tatsuya, Mito, Ikuo
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Fleck, Linda J.
• Application Number:
  US07/750,172
• Time in Patent Office: 771 Days
• Field of Search: 437/89, 437/126, 437/129, 437/133, 148/DIG. 26
• US Class Current: 438/24
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 33/0062 for devices with an active region comprising only III-V compounds
• CPC Class Codes: H01S 3/1055 one of the reflectors being constituted by a diffraction grating
• CPC Class Codes: H01S 5/026 Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06
• CPC Class Codes: H01S 5/0265 Intensity modulators intra-cavity modulators H01S5/0625
• CPC Class Codes: H01S 5/04256 characterised by the configuration
• CPC Class Codes: H01S 5/06256 with DBR-structure
• CPC Class Codes: H01S 5/11 Comprising a photonic bandgap structure
• CPC Class Codes: H01S 5/16 Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface H01S5/14 takes precedence
• CPC Class Codes: H01S 5/164 with window regions comprising semiconductor material with a wider bandgap than the active layer
• CPC Class Codes: H01S 5/2077 using lateral bandgap control during growth, e.g. selective growth, mask induced
• CPC Class Codes: H01S 5/227 Buried mesa structure ; Striped active layer
• CPC Class Codes: H01S 5/2272 grown by a mask induced selective growth
• CPC Class Codes: H01S 5/34306 emitting light at a wavelength longer than 1000nm, e.g. InP based 1300 and 1500nm lasers
• CPC Class Codes: H01S 5/34313 with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
• CPC Class Codes: H01S 5/3434 with a well layer comprising at least both As and P as V-compounds
• CPC Class Codes: Y10S 148/026 Deposition thru hole in mask

Abstract

A method for fabricating an optical semiconductor device includes the steps of forming at least two stripes of dielectric parallel to each other with a predetermined interval on a semiconductor substrate, growing a crystal selectively between the two stripes, and forming a multi-layer structure which is required to have a width determined by the crystal grown between the two stripes. In such a method, the width of the multi-layer structure including an active layer or a waveguide is controlled precisely, because there is no step of etching a semiconductor layer, so that the characteristics of the device may improve and the yield may increase.

Claims

1. A method for fabricating an optical semiconductor device, comprising the steps of:

forming a dielectric layer on a semiconductor substrate, said dielectric layer being formed as two dielectric stripes which are parallel to each other and defining a predetermined interval therebetween;

growing a crystal selectively on said semiconductor substrate, using said dielectric stripes as a mask, to form a multi layer structure having a width which is determined by said predetermined interval;

etching portions of said dielectric stripes to change the size of said predetermined interval; and

selectively growing an additional crystal between said predetermined interval after said etching step.

2. A method for fabricating an optical semiconductor device, comprising the steps of:

forming a dielectric layer on a semiconductor substrate, said dielectric layer being formed as two dielectric stripes which are parallel to each other and defining a predetermined interval therebetween;

growing a crystal selectively on said semiconductor substrate, using said dielectric stripes as a mask, to form a multi layer structure having a width which is determined by said predetermined interval;

etching a portion of each of said dielectric stripes which faces the other of said dielectric stripes to expose a portion of the surface of said dielectric substrate; and

growing a crystal selectively to form a clad layer on said semiconductor substrate on at least the area between said two dielectric stripes as etched.

3. A method for fabricating an optical semiconductor device, according to claim 2;

wherein said steps of growing a crystal is carried out by metalorganic vapor phase epitaxy.

4. A method for fabricating an optical semiconductor device, according to claim 2:

wherein said step of forming a dielectric layer is a step of forming an SiO₂ layer.

5. A method for fabricating an optical semiconductor device, according to claim 2:

wherein said multi-layer structure includes a layer selected from a group consisting of an active layer and a waveguide layer.

6. A method for fabricating an optical semiconductor device, comprising the steps of:

forming first and second regions on a semiconductor crystal substrate, said first region having a surface having diffraction lattices and said second region having a flat surface;

forming a multi-layer semiconductor substrate including a semiconductor guide layer on said fabricated surface of said semiconductor crystal substrate;

forming at least two stripes of dielectric layer sandwiching an optical waveguide region on said multi-layer semiconductor substrate, said stripes extending parallel to each other with a predetermined interval therebetween and each of said stripes having a width which is wider in said first region and is narrower in said second region;

forming a multi-layer semiconductor layer including an active layer by selective growth on a surface of said multi-layer semiconductor substrate including said optical waveguide region; and

forming a semiconductor laser and a semiconductor optical modulator in said first and second regions, respectively.

7. A method for fabricating an optical semiconductor device, comprising the steps of:

forming first to third regions on a semiconductor crystal substrate, each of said first and second regions having a flat surface and said third region having a surface having diffraction lattices;

forming a multi-layer semiconductor substrate including a semiconductor guide layer on said fabricated surface of said semiconductor crystal substrate;

forming at least two stripes of dielectric layer sandwiching an optical waveguide region on said multi-layer semiconductor substrate, said stripes extending parallel to each other with a predetermined interval therebetween and each of said stripes having a width which is wider in said first region and is narrow and the same in said second and third regions;

forming a multi-layer semiconductor layer including an active layer by selective growth on a surface of said multi-layer semiconductor substrate including said optical waveguide region; and

forming a light emission unit, a phase control unit and a wavelength variable braggy reflector in said first to third regions, respectively.