Low temperature germanium-silicon on insulator thin-film transistor
First Claim
1. A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region,contacts to said source and drain region, a gate dielectric overlying said channel region, anda conductive gate overlying said gate dielectric and said channel region, wherein said first layer comprising source, drain and channel regions is formed of a polycrystalline Gex Si1-x alloy, where 1>
- x>
0, and wherein said transistor conductive gate is formed of a Gey Si1-y alloy, where 1>
y>
0.
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Abstract
MOS transistors are formed in thin films of Ge/Si alloys (Gex Si1-x). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Gex Si1-x films are polycrystalline at temperatures for processing down to as below 400° C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600° C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400° to 500° C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500° C., and as low as 400° C., by using Gex Si1-x deposition and doping technology. The resulting transistors have significantly improved electrical characteristics compared to thin film transistors fabricated in silicon films utilizing standard processing techniques.
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Citations
7 Claims
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1. A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region,
contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, wherein said first layer comprising source, drain and channel regions is formed of a polycrystalline Gex Si1-x alloy, where 1> - x>
0, and wherein said transistor conductive gate is formed of a Gey Si1-y alloy, where 1>
y>
0.
- x>
-
2. A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region,
contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, said conductive gate being formed of a polycrystalline Gey Si1-y alloy, where 1>
-
5. A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, wherein said channel region is formed of a polycrystalline Gex Si1-x alloy wherein 1>
- x>
0, said transistor conductive gate being formed of a Gey Si1-y alloy, where 1>
y>
0. - View Dependent Claims (6, 7)
- x>
Specification