Low temperature germanium-silicon on insulator thin-film transistor

• US 5,250,818 A
• Filed: 03/01/1991
• Issued: 10/05/1993
• Est. Priority Date: 03/01/1991
• Status: Expired due to Term

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Saraswat, Krishna C., King, Tsu-Jae
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/663,092
• Time in Patent Office: 949 Days
• Field of Search: 357/2, 357/4, 357/23.1, 357/23.7, 357/23.2, 257/66, 257/70l412, 257/616
• US Class Current: 257/66
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

MOS transistors are formed in thin films of Ge/Si alloys (Ge_x Si_1-x). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Ge_x Si_1-x films are polycrystalline at temperatures for processing down to as below 400° C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600° C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400° to 500° C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500° C., and as low as 400° C., by using Ge_x Si_1-x deposition and doping technology. The resulting transistors have significantly improved electrical characteristics compared to thin film transistors fabricated in silicon films utilizing standard processing techniques.

Claims

1. A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region,

contacts to said source and drain region, a gate dielectric overlying said channel region, and

a conductive gate overlying said gate dielectric and said channel region, wherein said first layer comprising source, drain and channel regions is formed of a polycrystalline Ge_x Si_1-x alloy, where 1>

x>

0, and wherein said transistor conductive gate is formed of a Ge_y Si_1-y alloy, where 1>

y>

0.

2. A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region,

contacts to said source and drain region, a gate dielectric overlying said channel region, and

a conductive gate overlying said gate dielectric and said channel region, said conductive gate being formed of a polycrystalline Ge_y Si_1-y alloy, where 1>

y>

0.

3. The MOS thin film transistor as claimed in claim 2 wherein the value of y is at least 0.25.

4. The MOS thin film transistor as claimed in claim 2 wherein the value of y is at least 0.5.

5. A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, wherein said channel region is formed of a polycrystalline Ge_x Si_1-x alloy wherein 1>

x>

0, said transistor conductive gate being formed of a Ge_y Si_1-y alloy, where 1>

y>

0.

6. The MOS thin film transistor as claimed in claim 5 wherein the value of y is at least 0.25.

7. The MOS thin film transistor as claimed in claim 5 wherein the value of y is at least 0.5.