Field effect type thin film transistor having a plurality of gate electrodes

• US 5,250,835 A
• Filed: 12/20/1991
• Issued: 10/05/1993
• Est. Priority Date: 01/16/1991
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Casio Computer Company Limited
• Inventors: Izawa, Mitsuharu
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/812,578
• Time in Patent Office: 655 Days
• Field of Search: 357/23.1, 357/23.3, 357/23.7, 357/23.14, 357/41, 257/344, 257/408, 257/365, 257/66, 257/369
• US Class Current: 257/408
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

A thin film transistor includes a gate insulating film, a plurality of gate electrodes arranged on one surface of the gate insulating film, and a thin film semiconductor island formed on the other surface of the gate insulating film and having portions each corresponding to one of the gate electrodes. The island includes a source region in which ion impurities are diffused at high density and located at one end of the island, a drain region in which ion impurities are diffused at high density and located at the other end of the island, a first low impurity region in which ion impurities are diffused at lower density than that of the drain region and located between the drain region and one of the portions adjacent to the drain region, and a second low impurity region in which ion impurities are diffused at lower density than that of the drain region and located between at least one of the portions.

Claims

1. A thin film semiconductor device having a plurality of transistors comprising:

a thin film semiconductor island having a first zone and a second zone, said first and second zones being contiguously formed;

said island including;

a source region in which ion impurities are diffused to have a high density, said source region being disposed at an end portion of said first zone of said island;

a drain region in which ion impurities are diffused to have a high density, said drain region being disposed at an end portion of said second zone of said island;

said source region being disposed on said island at a side of said island that is opposite to said drain region;

a first low impurity region in which ion impurities are diffused and have a density that is lower than said high density of said drain region, said first low impurity region being disposed adjacent to said drain region in said second zone of said island;

a second low impurity region in which ion impurities are diffused to have a density that is lower than said high densities of said source and drain regions, said second low impurity region being disposed between said first low impurity regions and said source region;

a first channel region provided between said second low impurity region and said source region in said first zone of said island; and

a second channel region provided between said first and second low impurity regions in said second zone of said island;

a gate insulating film formed on said island;

a first gate electrode formed on said gate insulating film at a position on said first zone in said island that corresponds to a position of said first channel region in said island; and

a second gate electrode formed on said gate insulating film at a position on said second zone in said island that corresponds to a position of said second channel region in said island;

whereby;

(A) said source region, said first channel region and said second low impurity region that are respectively provided in said first zone of said island, are operationally coupled with said first gate electrode, to form a first thin film transistor; and

(B) said drain region, said first low impurity region, said second channel region and said second low impurity region that are respectively provided in said second zone of said island, are operationally coupled with said second gate electrode to form a second thin film transistor that is drivable when a gate voltage is applied to said second gate electrode independently of a driving of said first gate electrode of said first thin film transistor.

2. The thin film semiconductor device according to claim 1, wherein said first and second low impurity regions have ion impurity densities which are substantially equal to each other.

3. The thin film semiconductor device according to claim 1, wherein said thin film semiconductor island comprises polycrystalline silicon.

4. The thin film semiconductor device according to claim 1, wherein said thin film semiconductor device comprises a clocked inverter.

5. The thin film semiconductor device according to claim 1, wherein said thin film semiconductor device comprises an inverter.

6. A thin film semiconductor device having a plurality of transistors comprising:

a thin film semiconductor island having a first zone, a second zone, and a third zone disposed between said first and second zones, said first, second and third zones being contiguously formed, on said island;

said island including;

a first high dopant region in which ion impurities are diffused to have a high density, said first high density dopant region being disposed at an end portion of said first zone of said island;

a second high dopant region in which ion impurities are diffused to have a high density, said second high dopant region being disposed at an end portion of said second zone of said island;

said first high dopant region being disposed, in said island at a side of said island that is opposite to said second high dopant region in said island;

a first low dopant region in which ion impurities are diffused and have a density lower than said high density of said first high dopant region, said first low dopant region being disposed adjacent to said first high dopant region in said first zone of said island;

a second low dopant region in which ion impurities are diffused to have a density lower than said high density of said second high dopant region, said second low dopant region being disposed adjacent to said second high dopant region in said second zone of said island;

a third and fourth low dopant region in which ion impurities are respectively diffused to have a density lower than said densities of said first and second high dopant regions, said third and fourth low dopant regions being disposed between said first and second low dopant regions so as to be spaced apart from each other;

a first channel region provided between said first and said third low dopant regions in said first zone of said island;

a second channel region provided between said second and said fourth low dopant regions in said second zone of said island; and

a third channel region provided between said third and said fourth low dopant regions in said third zone of said island;

a gate insulating film formed on said island;

a first gate electrode formed on said gate insulating film at a position on said first zone in said island that corresponds to a position of said first channel region in said island;

a second gate electrode formed on said gate insulating film at a position on said second zone in said island that corresponds to said second channel region in said island; and

a third gate electrode formed on said gate insulating film at a position on said third zone in said island that corresponds to a position of said third channel region, in said island;

whereby;

(A) said first high dopant region, said first channel region and said third low dopant region, said first gate electrode, and said third low dopant region together form a first thin film transistor;

(B) said second high dopant region, said second channel region, said second low dopant region, said second gate electrode, and said fourth low dopant region together form a second thin film transistor; and

(C) said third gate electrode, said third channel region, said third low dopant region, and said fourth low dopant region, together form a third thin film transistor which is drivable, when a gate voltage is applied to said third gate electrode, independently of a driving to said first and second gate electrodes of said first and second thin film transistors, respectively.

7. The thin film semiconductor device according to claim 6, wherein said first, second, third and fourth low dopant regions have ion impurity densities which are substantially equal to each other.

8. The thin film semiconductor device according to claim 6, wherein said thin film semiconductor island comprises polycrystalline silicon.

9. The thin film semiconductor device according to claim 6, wherein said thin film semiconductor device comprises a NAND circuit.

10. The thin film semiconductor device according to claim 6, wherein said thin film semiconductor device comprises a NOR circuit.