Multichip integrated circuit modules

• US 5,250,843 A
• Filed: 09/08/1992
• Issued: 10/05/1993
• Est. Priority Date: 03/27/1991
• Status: Expired due to Fees

• Current Assignee: Integrated System Assemblies Corp.
• Original Assignee: Integrated System Assemblies Corp.
• Inventors: Eichelberger, Charles W.
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): MONIN, DONALD L JR
• Application Number:
  US07/942,105
• Time in Patent Office: 392 Days
• Field of Search: 357/74, 357/75, 357/80, 357/81, 174/52.2, 174/52.4, 257/692, 257/693, 257/687
• US Class Current: 257/692
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A multichip integrated circuit package comprises a substrate having a flat upper surface to which is affixed one or more integrated circuit chips having interconnection pads. A polymer encapsulant completely surrounds the integrated circuit chips. The encapsulant is provided with a plurality of via openings therein to accommodate a layer of interconnection metallization. The metallization serves to connect various chips and chip pads with the interconnection pads disposed on the chips. In specific embodiments, the module is constructed to be repairable, have high I/O capability with optimal heat removal, have optimized speed, be capable of incorporating an assortment of components of various thicknesses and function, and be hermetically sealed with a high I/O count. Specific processing methods for each of the various module features are described herein, along with additional structural enhancements.

Claims

1. A multichip integrated circuit package comprising:

a substrate having a flat upper surface;

a plurality of unpackaged integrated circuit chips disposed above said substrate'"'"'s flat upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate'"'"'s flat upper surface, said integrated circuit chips also each having at least one side surface;

an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate'"'"'s flat upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and

a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings, and so as to provide direct electrical connection to at least some of said interconnection pads through said openings, wherein a unitary package of multiple directly interconnected integrated circuit chips is produced.

2. The integrated circuit package of claim 1, wherein said encapsulant comprises a polymer.

3. The integrated circuit package of claim 2, wherein said encapsulant is selected from the group consisting of thermoplastic and thermoset materials.

4. The integrated circuit package of claim 1, wherein the substrate comprises material selected from the group consisting of glass, metal, ceramic, plastic, silicon and composites.

5. The integrated circuit package of claim 1, wherein the substrate comprises alumina.

6. The integrated circuit package of claim 1, further including:

a dielectric layer overlying said encapsulant and said interconnection conductors, said dielectric layer also including a plurality of via openings therein aligned with at least some of said interconnection conductors disposed on said encapsulant; and

a second plurality of interconnection conductors disposed above said dielectric layer and extending between at least some of the openings in said dielectric layer so as to provide electrical connection with interconnection pattern conductors disposed above said encapsulant.

7. The integrated circuit package of claim 6, wherein said dielectric layer, together with said second plurality of interconnection conductors, is removable.

8. The integrated circuit package of claim 7, wherein said dielectric layer comprises a solvent-sensitive layer.

9. The integrated circuit package of claim 1, further including:

a solvent-sensitive layer overlying said encapsulant and said interconnection conductors;

a dielectric layer overlying said solvent-sensitive layer, said dielectric layer and said solvent-sensitive layer including a plurality of via openings therein aligned with at least some of said interconnection pattern conductors disposed on said encapsulant; and

a second plurality of interconnection conductors disposed above said dielectric layer and extending between at least some of the openings in said dielectric layer so as to provide electrical connection with interconnection pattern conductors disposed on said encapsulant.

10. The integrated circuit package of claim 1, further comprising:

at least one preprocessed chip disposed on said substrate'"'"'s flat upper surface; and

wherein;

said encapsulant overlies said preprocessed chip, said encapsulant having a via opening therein to the upper surface of said preprocessed chip; and

said pattern of interconnection conductors is disposed above the upper surface of said encapsulant so as to extend between at least some of said via openings, including said opening over the upper surface of said preprocessed chip, so as to provide electrical connection to at least some of said integrated circuit chips and said preprocessed chip.

11. The integrated circuit package of claim 10, wherein said preprocessed chip is positioned near an edge of said multichip package and comprises an input output circuit.

12. The integrated circuit package of claim 10, wherein said preprocessed chip includes a series of conductive lands on a top surface thereof for wire bonding thereto, and wherein said encapsulant overlies only a portion of the top surface of said preprocessed chip and a portion of said conductive lands located thereon, said encapsulant having a via opening therein over at least one of said series of conductive lands, said pattern of interconnection conductors being disposed above the upper surface of said encapsulant so as to extend between at least some of said via openings, including said via opening over said at least one land of said preprocessed chip, to provide electrical connection to at least some of said plurality of integrated circuit chips and said preprocessed chip.

13. The integrated circuit package of claim 10, wherein said preprocessed chip comprises a tiered power and ground bussing structure, said bussing structure including a power strip and a ground strip, and wherein said encapsulant overlies said power and ground bussing structure and has at least one via opening therein to each of said power and ground strips, said pattern of interconnection conductors being disposed above the upper surface of said encapsulant so as to provide electrical connection between said power and ground strips of said preprocessed chip and at least some of said integrated circuit chips.

14. The integrated circuit package of claim 10, wherein said preprocessed chip comprises a termination resistor, said resistor having pads on the upper surface thereof, and wherein said encapsulant'"'"'s via openings and said pattern of interconnection conductors are disposed to provide electrical connection to said termination resistor and at least some of said integrated circuit chips.

15. The integrated circuit package of claim 10, wherein an adhesive layer is disposed on said substrate'"'"'s flat upper surface between said plurality of integrated circuit chips and said substrate.

16. The integrated circuit package of claim 1, wherein an adhesive layer is disposed on said substrate'"'"'s flat upper surface between said plurality of integrated circuit chips and said substrate, and further comprising a termination resistor array, said resistor array being disposed between said substrate and said adhesive layer, and wherein said adhesive layer has via openings therein aligned with selected ones of said plurality of via openings in said encapsulant and with selected electrical contact points in said termination resistor array.

17. The integrated circuit package of claim 16, wherein each termination resistor array is positioned below one of said plurality of integrated circuit chips.

18. The integrated circuit package of claim 1, further comprising an array of electrical contact pads on an upper surface of said package, said array of contact pads being electrically coupled via at least one level of interconnection conductors to at least some of said integrated circuit interconnection pads.

19. The integrated circuit package of claim 18, wherein said array of electrical contact pads on the upper surface of said package provide electrical interface to circuitry external to said package, and wherein said substrate has a lower surface, said lower substrate surface providing a thermal interface for dissipation of heat generated by said integrated circuit chips.

20. The integrated circuit package of claim 19, wherein said substrate'"'"'s lower surface comprises a lower surface of said integrated circuit package.

21. The integrated circuit package of claim 1, wherein said upper surface of said encapsulant is flat and approximately 1-2 mils from the top surface of said integrated circuit chips.

22. The integrated circuit package of claim 1, wherein a thin continuous adhesive film is disposed on said substrate'"'"'s flat upper surface between said plurality of integrated circuit chips and said substrate.

23. The integrated circuit package of claim 1, wherein said plurality of integrated circuit chips each have a predetermined thickness, said predetermined thickness being in the range of 4 mils to 8 mils.

24. The integrated circuit package of claim 18, wherein said array of electrical contact pads on the upper surface of said package substantially covers said package'"'"'s upper surface, at least some of said array of contact pads being disposed over other than said plurality of integrated circuit chips.

25. The integrated circuit package of claim 1, further comprising:

a signal plane disposed above the top surfaces of said plurality of integrated circuit chips; and

a substantially uninterrupted conductive plane also disposed above the top surfaces of said integrated circuit chips, said substantially uninterrupted conductive plane being substantially parallel to said signal plane.

26. The integrated circuit package of claim 25, further comprising:

at least one termination resistor disposed on the upper surface of said substrate; and

connection means for coupling said signal plane to said at least one termination resistor.

27. The integrated circuit package of claim 1, wherein at least two substantially uninterrupted conductive planes are disposed above the top surfaces of said integrated circuit chips, each of said conductive planes being substantially parallel to said signal plane.

28. The integrated circuit package of claim 27, wherein one of said conductive planes comprises a ground plane and one of said conductive planes comprises a power plane.

29. The integrated circuit package of claim 28, wherein each chip of said plurality of integrated circuit chips has a predetermined thickness, said predetermined thickness being in the range of 4 mils to 8 mils.

30. The integrated circuit package of claim 28, wherein said ground plane is disposed between said signal plane and the top surfaces of said integrated circuit chips.

31. The integrated circuit package of claim 28, wherein said ground plane and said power plane are disposed in close, parallel opposing relation to each other, and further comprising a dielectric material disposed between said power plane and said conductive plane.

32. The integrated circuit package of claim 31, wherein said signal plane is spaced a distance y from the top surfaces of said integrated circuit chips and wherein said power plane is spaced a distance x from said ground plane, distance y being greater than distance x.

33. Multichip integrated circuit package comprising:

a circuit component, said component having an upper surface with at least one interconnection pad thereon;

a substrate having an upper surface and a lower surface, said substrate including a hole therein extending from said upper substrate surface to said lower substrate surface, said substrate hole being sized to accommodate said circuit component therein;

at least one integrated circuit chip disposed above said substrate'"'"'s upper surface, said integrated circuit chip having at least one interconnection pad on a top surface thereof, the top surface of said at least one integrated circuit chip being in a plane substantially parallel to said substrate'"'"'s upper surface, said integrated circuit chip also having at least one side surface;

said component being positioned within said substrate hole such that said component'"'"'s upper surface is substantially parallel to said substrate'"'"'s upper surface;

an encapsulant surrounding said at least one integrated circuit chip including said top surface and said at least one side surface thereof, and contacting at least the upper surface of said circuit component, said encapsulant having an upper surface above the tops of the integrated circuit chip and the circuit component and having a plurality of via openings therein, said openings being aligned with at least some of said chip and component interconnection pads; and

a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection to at least some of said interconnection pads through said openings.

34. The integrated circuit package of claim 33, wherein a plurality of integrated circuit chips are disposed on said substrate'"'"'s upper surface, each of said circuit chips having at least one interconnection pad on the top surface thereof.

35. The integrated circuit package of claim 34, wherein said substrate upper surface is flat.

36. The integrated circuit package of claim 34, wherein the top surfaces of said integrated circuit chips and the upper surface of said circuit component are substantially coplanar, said plane being parallel to the upper surface of said substrate.

37. The integrated circuit package of claim 36, further comprising means for securing said circuit component within said substrate hole such that the upper surface of said circuit component remains substantially in the same plane as the top surfaces of said integrated circuit chips.

38. The integrated circuit package of claim 34, wherein multiple substrate holes are provided, each of said through holes being sized to accommodate one of a plurality of circuit components.

39. The integrated circuit package of claim 34, wherein said substrate has a lower surface, and said package further comprises a well within said substrate disposed on said substrate'"'"'s lower surface, said well being sized to accommodate a circuit component such that said component resides within said substrate well, said circuit component being electrically coupled to the upper surface of said substrate by metallized through holes extending through said substrate from said well to said upper substrate surface.

40. The hermetically packaged module of claim 39, wherein said multichip module has at least one side surface and wherein said sealing ring is attached to said at least one module side surface.

41. The hermetically packaged module of claim 40, wherein said lid'"'"'s cover plate is ceramic.

42. The hermetically packaged module of claim 41, wherein said conductive means comprises a metallization extending through said cover plate openings.

43. The hermetically packaged module of claim 42, wherein said lid cover plate includes gold pads on each side thereof, each of said gold pads contacting one of said metallized cover plate openings.

44. A multichip integrated circuit package comprising:

a substrate having an upper surface and a lower surface, said substrate having a well disposed on the lower surface thereof, said well being sized to accommodate a circuit component such that said component resides entirely within said substrate well;

at least one integrated circuit chip disposed above said substrate'"'"'s upper surface, said integrated circuit chip having at least one interconnection pad on a top surface thereof, the top surface of said at least one integrated circuit chip being in a plane substantially parallel to said substrate'"'"'s upper surface, said integrated circuit chip also having at least one side surface;

means for electrically coupling a circuit component disposed within said substrate well with the upper surface of said substrate;

an encapsulant surrounding said at least one integrated circuit chip including said top surface and said at least one side surface thereof, and the upper surface of said substrate, said encapsulant having an upper surface above the top of said integrated circuit chip and having a plurality of via openings therein, said openings being aligned with at least some of said chip interconnection pads and said electrical means for coupling said circuit component disposed within said well to the upper surface of said substrate; and

a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection through said openings to at least some of said interconnection pads and said circuit component disposed within said well.

45. The integrated circuit package of claim 44, wherein said electrical coupling means comprises at least two metallized through holes extending through said substrate from said well to said upper substrate surface.

46. The integrated circuit package of claim 44, wherein a plurality of integrated circuit chips are disposed on said substrate'"'"'s upper surface, each of said circuit chips having at least one interconnection pad on the top surface thereof.

47. The integrated circuit package of claim 46, wherein said substrate'"'"'s upper surface is flat.

48. A hermetically packaged multichip integrated circuit module comprising:

a multichip module including;

a substrate having an upper surface;

a plurality of unpackaged integrated circuit chips disposed above said substrate'"'"'s upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate'"'"'s upper surface, said integrated circuit chips also each having at least one side surface;

an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate'"'"'s upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and

a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings, and so as to provide direct electrical connection to at least some of said interconnection pads through said openings wherein a unitary module having multiple directly interconnected integrated circuit chip is produced, said pattern of interconnection conductors including at least one connection pad;

a lid including an electrically insulating cover plate having a plurality of openings therethrough;

conductive plugs hermetically disposed within said cover plate openings;

means for electrically connecting at least one of said conductive plugs of said cover plate with at least one of said connection pads of said pattern of interconnection conductors; and

means for hermetically sealing said lid about said single multichip module with said at least one conductive plug in electrical contact with said at least one connection pad of said pattern of interconnection conductors.

49. The hermetically packaged module of claim 48, wherein said means for electrically connecting said at least one conductive plug with said at least one connection pad of said pattern of interconnection conductors comprises an array of button contacts disposed between said cover plate and the upper surface of said multichip module.

50. A hermetically packaged multichip integrated circuit module comprising:

a multichip module including;

a substrate having an upper surface;

a plurality of unpackaged integrated circuit chips disposed above said substrate'"'"'s upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate'"'"'s upper surface, said integrated circuit chips also each having at least one side surface;

an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate'"'"'s upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and

a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings and so as to provide direct electrical connection to at least some of said interconnection pads through said openings wherein a unitary module having multiple directly interconnected integrated circuit chips is produced, said pattern of interconnection conductors including at least one connection pad;

a lid including an electrically insulating cover plate having a plurality of openings extending therethrough, said cover plate openings each being aligned with a connection pad on said pattern of interconnection conductors;

conductive means hermetically disposed within each of said cover plate openings, at least one of said conductive means being in electrical contact with one of said connection pads of said pattern of interconnection conductors; and

means for hermetically sealing said lid about said multichip module with said at least one conductive means in electrical contact with said connection pads of said pattern of interconnection conductors.

51. The hermetically packaged module of claim 50, further including a sealing ring disposed about said module and sealed to said cover plate.

52. The hermetically packaged module of claim 51, wherein a lower surface of said module'"'"'s substrate is secured to said sealing ring.

53. The hermetically packaged module of claim 51, wherein said module has at least one side surface and wherein said sealing ring is sealed to said at least one module side surface.

54. The hermetically packaged module of claim 50, wherein said module'"'"'s substrate forms a portion of said hermetic packaging.