Variable pulse width phase detector
First Claim
1. In a phase locked loop for synchronizing to a serial data bit stream including a VCO (voltage controlled oscillator) generating a bit clock, a phase detector for comparing said serial data bit stream to said bit clock and for passing an error signal to a low pass filter coupled to said phase detector, said low pass filter connected to said VCO for correcting the frequency of said VCO responsive to said filter output,means to also couple said low pass filter output back to said phase detector, and wherein said phase detector includes a time delay circuit responsive to said low pass filter output.
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Accused Products
Abstract
A phase detector (1) for a phase locked loop (PLL) for bit clock retrieval where the phase detector employs a plurality of variable unit delays (20,21) and has a constant gain region that is a percentage of the clock period over an extended frequency range of the VCO enabling a single (PLL) chip to operate for several applications at widely different frequencies.
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Citations
11 Claims
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1. In a phase locked loop for synchronizing to a serial data bit stream including a VCO (voltage controlled oscillator) generating a bit clock, a phase detector for comparing said serial data bit stream to said bit clock and for passing an error signal to a low pass filter coupled to said phase detector, said low pass filter connected to said VCO for correcting the frequency of said VCO responsive to said filter output,
means to also couple said low pass filter output back to said phase detector, and wherein said phase detector includes a time delay circuit responsive to said low pass filter output.
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2. In a phase detector for a phase locked loop including a serially connected phase detector, low pass filter and VCO (voltage controlled oscillator), said phase detector comprising:
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first terminal means to receive a serial data bit stream; second terminal means to receive a bit clock from said VCO; third terminal means to receive an analogue voltage from said low pass filter; variable time delay means connected to said first terminal and being responsive to said analogue voltage from said low pass filter; and said phase detector having a constant gain region as a fixed percentage of frequency, said phase detector including means to generate a pump up pulse and a pump down pulse by combinatorial logic, the sum of the time duration of said pump up and pump down pulses being a constant percentage of the period of said bit clock over the entire frequency range of said VCO. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9)
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10. A method for providing a variable delay of an input waveform comprising:
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inputting said input waveform to a first and second delay line in parallel; applying the output VD1 of said first delay line to a first port of an adder/weighter circuit; applying the output VD2 of said second delay line to a second port of said adder/weighter;
said first output VD1 being delayed by time td with respect to said second output VD2;weighting output VD1 by α
to form V1 in said adder/weighter circuit;weighting output VD2 by (1-α
) to form V2 in said adder/weighter circuit;adding V1 +V2 to form V3 in said adder/weighter; and outputting V3, where V3 is delayed with respect to said second output VD2 by td (1-α
) wherein α
is a variable weighting factor. - View Dependent Claims (11)
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Specification