Circuit simulation interface methods

• US 5,251,159 A
• Filed: 03/20/1991
• Issued: 10/05/1993
• Est. Priority Date: 03/20/1991
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Rowson, James A.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US07/672,257
• Time in Patent Office: 930 Days
• Field of Search: 364/578, 364/488, 364/490, 395/157, 395/500
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: Y10S 715/97 Instrumentation and component modelling, e.g. interactive control panel

Abstract

In a process for analyzing simulation results and providing such results in terms that are familiar to the circuit designer, user-defined primitives, or tiles, are used to reduce large quantities of simulation data into meaningful information. Incremental simulation results which are acquired during the simulation are distributed to the appropriate tiles using a specialized data structure that includes reporting simulation results from the simulator using a node index.

Claims

1. Using a computer, a method for presenting to a user intermediate and final results of computer simulation and analysis of designs for integrated circuits, comprising the steps of:

accepting a user definition of a user-defined control panel display composed of tiles including at least one of;

a datapath compiler tile depicting a datapath and, apart from depiction of said datapath, representing data flow through said datapath in a current logic state;

a logic synthesizer tile depicting a logic state diagram and representing a current logic state;

an analytical results tile depicting a functional relationship between two circuit variables; and

a specification tile depicting specified circuit parameter limits and representing a degree to which said specified circuit parameter limits have been met;

said method comprising the further steps of;

causing a circuit design simulation to be executed on said computer;

indexing simulation results for distribution to appropriate tiles of the user-defined control panel display;

distributing simulation results to appropriate tiles of a user-defined control panel display; and

,

modifying at least one tile to illustrate the simulation results.

2. A method according to claim 1 wherein two or more tiles are modified with the same simulation results.

3. A method according to claim 1 wherein at least one tile annotates simulation results onto a logic synthesizer input.

4. A method according to claim 1 wherein at least one tile annotates simulation results onto a silicon compiler input.

7. A method according to claim 1 wherein at least one tile represents a plot of simulation results.

8. A method according to claim 7 wherein the plot is created by modifying the simulation result via a user defined calculation.

9. A method according to claim 1 wherein at least one tile checks circuit design specifications.

10. A method according to claim 9 wherein pre-defined delay constraints are used to verify timing specifications of the circuit design.

5. A method according to claim wherein at least one tile is created by selecting a drawing in response to the simulation results, the drawing being further annotated during the step of modifying.

6. A method according to claim wherein the drawing is selected from among a plurality of drawings entered by the user prior to the simulation.

11. A method of analyzing the results of an electronic circuit design simulation, comprising the steps of:

defining characteristics of the tiles designed to display electronic circuit simulation results using predetermined formats, said tiles including at least one of;

a datapath compiler tile depicting a datapath and, apart from depiction of said datapath, representing data flow through said datapath in a current logic state;

a logic synthesizer tile depicting a logic state diagram and representing a current logic state;

an analytical results tile depicting a functional relationship between two circuit variables; and

a specification tile depicting specified circuit parameter limits and representing a degree to which said specified circuit parameter limits have been met;

said method comprising the further steps of;

interpreting simulation results into user defined text or pictures according to said defined characteristics of said tiles; and

modifying at least one of the tiles using the interpreted simulation results.

12. A method according to claim 11 wherein the characteristics represent a user defined calculation routine.

13. A method according to claim 11 wherein the characteristics represent a user defined set.

14. A method according to claim 11 wherein the characteristics represent user defined timing constraints.

15. A method according to claim 11 wherein the characteristics represent user defined annotations which are added to the at least one tile.

16. Using a computer, a method for presenting to a user intermediate and final results of computer simulation and analysis of designs for integrated circuits, comprising the steps of:

accepting a user definition of a user-defined control panel display composed of tiles including at least one of;

a datapath compile tile depicting a datapath and, apart from depiction of said datapath, representing data flow through said datapath in a current logic state;

a logic synthesizer tile depicting a logic state diagram and representing a current logic state;

an analytical results tile depicting a functional relationship between two circuit variables; and

a specification tile depicting specified circuit parameter limits and representing a degree to which said specified circuit parameter limits have been met;

said method comprising the further steps of;

causing a circuit design simulation to be executed on said computer;

indexing simulation results for distribution to appropriate tiles of the user-defined control panel display;

distributing simulation results to appropriate tiles of a user-defined control panel display; and

,

modifying at least one tile to illustrate the simulation results.

17. A method according to claim 16 wherein the sub-field information identifies human readable language for modifying the at least one tile.

18. A method according to claim 16 wherein the step of modifying further includes a step of decoding simulation results into human readable text for annotation on the drawing.