Single receiver for receiving wireless transmission of signals is for use with a serial two-conductor data bus

• US 5,251,235 A
• Filed: 09/24/1991
• Issued: 10/05/1993
• Est. Priority Date: 06/14/1988
• Status: Expired due to Fees

• Current Assignee: Bengt Henoch
• Original Assignee: Bengt Henoch
• Inventors: Henoch, Bengt
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/764,124
• Time in Patent Office: 742 Days
• Field of Search: 375/17, 375/20, 375/21, 375/22, 375/106, 375/111, 375/113, 360/51, 379/55, 455/41, 370/78, 370/100.1, 381/79
• US Class Current: 375/259
• CPC Class Codes: H04J 7/02 in which the polarity of the amplitude is characteristic
• CPC Class Codes: H04L 27/24 Half-wave signalling systems

Abstract

An arrangement for wireless transmission of signals using a serial two-conductor data bus, the arrangement including a clock conductor and a data conductor connected to a transmitter, a receiver and a demodulator, the transmitter including an oscillator, and further including a modulator which effects modulating the oscillator generated signal in dependence on the clock conductor signal and the data conductor signal respectively. The modulator (3) is operative in carrying out on the oscillator generated signal two significant, separate modulation steps which do not coincide in time, thereby to form two mutually independent signal channels (4,8;5,10), of which a first channel (4,8) is intended for data signals and the other channel (5,10) is intended for the clock signals. The demodulator (6) is operative in demodulating one thus modulated signal received by the receiver (2) and in recreating the aforementioned two signals, and also in that the demodulator has an output (9) for a clock conductor and an output (7) for a data conductor.

Claims

1. A single receiver comprising:

a demodulator, an output which is a serial, two-conductor data bus and input means to receive a wireless transmission of a modulated carrier signal from a transmitter that uses an oscillator to generate and transmit an alternating carrier signal which has been modulated by independent clock signals and data signals from a serial, two-conductor data bus input which has data signals that have a positive and a negative flank which respectively do not coincide with a positive or negative flank of the clock signals, and the modulated carrier signal, before transmission, having been modulated in dependence on the signal on the input clock conductor and in dependence on the signal on the input data conductor respectively, so that the transmitted carrier signal includes two significant, mutually independent, separate signal channels, which do not coincide in time, the first channel being caused by modulation steps on one of the groups of positive half cycles and negative half cycles of the alternating carrier signal being transmitted and the second channel being caused by modulation steps on the other of the groups of half cycles, and the first channel being for modulations representing data signals from the input data signal conductor and the second channel being for modulations representing clock signals from the input clock signal conductor and wherein the steps of the modulations of the carrier signal representing the clock signals are out-of-phase with the steps of the modulations of the carrier signal representing the data signals; and

said receiver demodulator comprising means to demodulate the transmitted modulated, oscillator generated carrier signal received by the single receiver and to recreate independent clock and data signals corresponding to the independent clock and data signals conducted from the input serial, two-conductor data bus to the transmitter, and which do not coincide in time; and

further comprising that said demodulator has a clock conductor output for said recreated clock signal and a data conductor output for said recreated data signal, said clock conductor output and said data conductor output being connected to the said output serial two-conductor data bus.

2. A receiver as defined in claim 1, characterised in that wireless receiving of the modulated carrier signal is effected with an inductive transmission device having at least two adjacent coils and where the single receiver includes one of said two coils.

3. A receiver according to claim 1, further comprising:

a diode type of rectifying bridge connected to said receiver input means; and

said demodulator includes two logic circuits with outputs, of which a first of said logic circuits is connected across a first diode in said rectifying bridge such as to cause said first diode to take out the positive half cycles of the received modulated carrier signal, and of which a second of said logic circuits is connected across a second diode in said rectifying bridge such as to cause said second diode to take out the negative half cycles of the received modulated carrier signal; and

further in that said logic circuits are arranged to produce on their respective said outputs, a pulse train corresponding to the positive and the negative half cycles respectively; and

wherein the demodulator includes circuits for separating modulated positive half cycles from modulated negative half cycles.

4. A receiver as defined in claim 3, wherein said demodulator includes two single-step counters, said outputs of the two said logic circuits are connected to the inputs of said two single-step counters in a manner such to obtain a first characteristic signal on the output of a first of said single-step counters when a positive half cycle of the carrier signal is modulated, and such as to obtain a second characteristic signal on the output of the other of said single-step counters when a negative half cycle of the carrier signal is modulated.

5. An arrangement according to claim 4, characterised in that said outputs of said logic circuits are connected to a trigger circuit which comprises an OR-gate, a low-pass filter and an inverting circuit, the output of said trigger circuit being connected to two latch-circuits, wherein an input of one of said latch-circuits is connected to the output of the first said single-step counter, and wherein the in input of the other of said latch-circuits is connected to the output of said other single-step counter, and the outputs of the two latch circuits provide the recreated clock and data signals.

6. A single receiver comprising:

a demodulator, an output which is a serial, two-conductor data bus and input means to receive a wireless transmission of a modulated carrier signal from a transmitter that uses an oscillator to generate and transmit an alternating carrier signal which has been modulated by independent clock signals and data signals from a serial, two-conductor data bus input which has data signals that have a positive and a negative flank which respectively do not coincide with a positive or negative flank of the clock signals, and the modulated carrier signal, before transmission, having ben modulated in two steps, one step being representative of the signal on the input clock conductor and the other step being representative of the signal on the input data conductor respectively, so that the transmitted carrier signal includes two significant, mutually independent, different and separate modulated steps on the oscillating carrier signal which do not coincide in time, a first of the two different modulation steps being a transmission of the carrier signal over a predetermined short time period and the second of the two different modulation steps being a transmission of the carrier signal over a predetermined long time period, of which periods the short time period is significantly shorter than the duration of a given, predetermined reference time and the long time period is significantly longer than the reference time, and said receiver demodulator comprising means to demodulate the transmitted modulated, oscillator generated carrier signal received by the single receiver and to recreate independent clock and data signals corresponding to the independent clock and data signals conducted from the input serial, two-conductor data bus to the transmitter, and which do not coincide in time; and

further comprising that said demodulator has a clock conductor output for said recreated clock signal and a data conductor output for said recreated data signal, said clock conductor output and said data conductor output being connected to the said output serial two-conductor data bus.

7. A receiver as defined in claim 6, wherein the oscillator produced alternating carrier frequency is high in relation to data pulse speed, and said receiver has means which utilizes the carrier frequency as said predetermined reference time.

8. A receiver as defined in claim 6, including a rectifier which receives the modulated carrier signal and recreates the modulations on the carrier signal and wherein said receiver demodulator includes a time comparison circuit constructed to compare the pulse length of the various pulses received with said reference time;

and in that said receiver demodulator also includes said data conductor and clock conductor outputs and produces a data conductor signal on a first of said two outputs and produces a clock conductor signal on the other of said two outputs.

9. A receiver according to claim 8, characterised in that said receiver demodulator rectifier is a detector diode and said time comparison circuit includes a multivibrator and an RC-circuit.

10. A receiver as defined in claim 9, wherein said demodulator includes two flip-flop circuits and a detector, the output of said multivibrator and the output of said detector diode are connected, respectively, to the inputs of said two flip-flop circuits, said detector is connected between the output of said detector diode and the inputs of said two flip-flop circuits;

said flip-flop circuits being adapted to be triggered by said detector upon detection of flanks in the signal from both of the multivibrator and detector diode outputs;

said flip-flop circuits being operative to recreate the clock and data signals which were conducted from the input serial two-conductor data bus to the transmitter, and of which flip-flop circuits, one circuit is operative to produce the recreated data signal and the other circuit is operative to produce the recreated clock signal.