Apparatus and method for neural processing

• US 5,251,287 A
• Filed: 01/06/1993
• Issued: 10/05/1993
• Est. Priority Date: 05/22/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pechanek, Gerald G., Vassiliadis, Stamatis
• Primary Examiner(s): MacDonald, Allen R.
• Application Number:
  US08/000,915
• Time in Patent Office: 272 Days
• Field of Search: 395/24, 395/27
• US Class Current: 706/26
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/10 Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Abstract

The neural computing paradigm is characterized as a dynamic and highly computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture for a Scalable Neural Array Process (SNAP) which uses a unique interconnection and communication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP'"'"'s packaging and expansion capabilities are addressed, demonstrating SNAP'"'"'s scalability to larger networks. The array processor is made up of multiple sets of orthogonal interconnections and activity generators. Each activity generator is responsive to an output signal in order to generate a neuron value. The interconnection structure also uses special adder trees which respond in a first state to generate an output signal and in a second state to communicate a neuron value back to the input of the array processor.

Claims

1. A scalable neural array processor, comprising a plurality of sets of interconnection structures and activity generators, a portion of said plurality of sets being orthogonal to a remaining portion of said plurality of sets, each said activity generator including means responsive to an output signal from one of said interconnection structures to generate a neuron value.

2. The neural array processor of claim 1, wherein:

said interconnection structure of at least one of said sets includes an adder tree having a first state responsive to a plurality of inputs to generate said output signal and a second state for communicating said neuron value back to said inputs;

and wherein said activity generator of said at least one of said sets has a first state, concurrent with said first state of said adder trees, for generating said neuron value and a second state, concurrent with said second state of said adder trees, for communicating said neuron value back to said interconnection structure of said at least one of said sets;

and further comprising control means for selectively activating said first and second states of said adder tree and said activity generator of said at least one of said sets.