Power controller for permitting multiple processors to power up shared input/output devices and inhibit power down until all processors have ceased service with the I/O devices

• US 5,251,320 A
• Filed: 05/25/1990
• Issued: 10/05/1993
• Est. Priority Date: 05/25/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zielinski, Edward J., Kuzawinski, Mark J.
• Primary Examiner(s): Anderson, Lawrence E.
• Assistant Examiner(s): GECKIL, MEHMET B
• Application Number:
  US07/528,974
• Time in Patent Office: 1,229 Days
• Field of Search: 395/750, 364/707
• US Class Current: 713/324
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A shared power controller for a rack of interface devices which are shared among a plurality of processor units. The shared power controller may be commanded into a power up mode by any connected central processor via its system power interface. A power down of a connected rack of interface units may, however, only be effected when all the connected CPU units enter a power down mode. A system power controller provides both remote and local operation such that diagnosis and analysis of problems may be effected locally at each rack of input/output devices.

Claims

1. In a multiprocessor system for data processing having shared input/output devices, a shared power controller for enabling said devices comprising:

a plurality of input connections of a plurality of control modules for receiving control signals from a system power interface of each processor;

a plurality of switching devices included within the control modules for supplying a first control signal to an output module for indicating a power up command in response to a POWER PICK signal and POWER HOLD signal received from said input connections;

a relay means included in said output module for supplying a second control signal to an external power control compartment, coupled with said shared input/output devices when any one of said switching devices is supplying said first control signal indicating a power up command and maintaining said second control signal as long as any one of said switching devices is asserting a first control signal, and means for supplying a pulse output signal to said external power control compartment when all of said switching devices are not supplying a power command, whereby said input/output devices are initially powered up when any one of said processor system power interfaces issues a POWER PICK signal, and is subsequently powered down only when none of said processor system power interfaces generates a POWER PICK or POWER HOLD signal; and

,

means located at a rack of said shared input/output devices for implementing a self-test of shared input/output devices which asserts a power pick signal to said plurality of switching means for generating a power up command in a local mode of operation when none of said processors are accessing said shared input/output devices.

2. The shared power controller of claim 1 wherein each of said plurality of switching devices comprises a relay responsive to a respective system power interface POWER PICK signal and which provides a UNIT POWER COMPLETE signal to a respective interface.

3. The system shared power controller of claim 1 wherein said relay means receives a signal KLX for enabling said relay means to supply a control signal to said power control compartment.