Semiconductor package
First Claim
Patent Images
1. A semiconductor package comprising:
- a die attach flag, wherein the die attach flag has an upper surface and a lower surface;
a plurality of leads which are electrically isolated from the die attach flag;
a number of tie bars which are coupled to the die attach flag;
upward angled flanges formed at edges of the die attach flag between each of the tie bars;
a semiconductor chip mounted on the upper surface of the die attach flag;
means for electrically coupling the plurality of leads to selected locations of the semiconductor chip; and
a plastic encapsulation covering the semiconductor chip, the means for electrical coupling, the upper surface of the die attach flag, the flange, and portions of the leads, wherein the lower surface of the die attach flag is exposed and forms a lower surface of the semiconductor package.
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Accused Products
Abstract
A semiconductor package is provided having a die attach flag (12) with integral flanges (13) which prevent high pressure plastic encapsulant (18) from escaping or entering between the die attach flag (12) and a mold cavity plate (15) during encapsulation. The die attach flag (12) is held flush against the cavity plate (15) by the packing pressure of the encapsulant (18) during low pressure stages of the encapsulation process. Plastic flowing along the flange (13) solidifies more rapidly than plastic in the body of the semiconductor package, thereby damming plastic flow at the edges of the die attach flag (12) during high pressure stages of the encapsulation process.
36 Citations
12 Claims
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1. A semiconductor package comprising:
- a die attach flag, wherein the die attach flag has an upper surface and a lower surface;
a plurality of leads which are electrically isolated from the die attach flag;
a number of tie bars which are coupled to the die attach flag;
upward angled flanges formed at edges of the die attach flag between each of the tie bars;
a semiconductor chip mounted on the upper surface of the die attach flag;
means for electrically coupling the plurality of leads to selected locations of the semiconductor chip; and
a plastic encapsulation covering the semiconductor chip, the means for electrical coupling, the upper surface of the die attach flag, the flange, and portions of the leads, wherein the lower surface of the die attach flag is exposed and forms a lower surface of the semiconductor package. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- a die attach flag, wherein the die attach flag has an upper surface and a lower surface;
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10. A semiconductor package comprising:
- a die attach flag having a first surface and a second surface, wherein the second surface is exposed;
a semiconductor chip attached to the first surface of the die attach flag;
upwardly angled flanges formed at all outer edges of the die attach flag; and
a molded plastic encapsulation in which the semiconductor chip, the flanges, and the first surface of the die attach flag are embedded. - View Dependent Claims (11, 12)
- a die attach flag having a first surface and a second surface, wherein the second surface is exposed;
Specification