Subarray architecture with partial address translation

• US 5,253,203 A
• Filed: 01/11/1993
• Issued: 10/12/1993
• Est. Priority Date: 04/11/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Partovi, Hamid, Case, Michael A.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US08/002,689
• Time in Patent Office: 274 Days
• Field of Search: 365/189, 365/189.01, 365/189.02, 365/230.02, 365/230.03, 365/51, 365/63, 364/200 MS File, 364/900 MS File
• US Class Current: 365/189.02
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

The physical organization of a memory cell array in an integrated circuit cache memory system is different from its logical organization because the bit lines of the array are divided into segments to physically divide the memory cell array into sub-arrays, and multiplexing the bit line segments of groups of neighboring bit lines are multiplexed to respective data lines. "Early" address bits control row decoders which select a row of memory cells in each sub-array to assert data signals on the bit line segments in each sub-array. "Late" address bits control the multiplexing of the data signals on the bit line segments to the data lines. By segmenting the bit lines, the number of "late" address bits is increased relative to the number of "early" address bits to increase the memory access speed in data processing systems that employ virtual addressing but store data in cache memory in association with physical addresses. The "late" address bits, for example, are a translated portion of a virtual address translated by a translation buffer, and the "early" address bits are an untranslated portion of the virtual address. Routing problems are avoided by extending the data lines in parallel with the bit lines over regions of the integrated circuit substrate allocated to the memory cells in the array, and forming the data lines in a metalization layer separate from and over a metalization layer of the bit lines. Each data line is multiplexed to multiple bit line segments to eliminate a final multiplexer to input/output lines.

Claims

1. An integrated circuit cache memory system on a semiconductor substrate, said cache memory system having an array of rows and columns of memory cells, word lines extending along the rows of memory cells, bit lines extending along the columns of memory cells, and an address decoder decoding row addresses to assert select signals on addressed ones of said word lines, each memory cell including means for asserting a stored information signal on the bit line along the column of said each memory cell when said address decoder asserts a select signal on the word line along the row of said each memory cell, said cache memory system having one set of outputs from some of said bit liens, and column multiplexing others of said bit lines to another set of outputs, wherein the improvement comprises

said array being physically subdivided into a plurality of sub-arrays of neighboring rows of memory cells, the sub-arrays each having rows addressed by said row addresses, each bit line being discontinuous between the sub-arrays so that each bit line has a bit line segment extending along a column in each of the sub-arrays, and each of said memory cells in each column of each sub-array has a connection to the bit line segment extending along said each column of said each sub-array, and said memory system further including data lines for conveying information signals from said bit line segments to said outputs, said data lines extending over regions of said semiconductor substrate allocated to said memory cells without connections to said memory cells in the array, and said memory system further includes sub-array multiplexing means responsive to a sub-array address for multiplexing information signals on said bit line segments of an addressed one of said sub-arrays to said data liens, wherein said data lines include one data line connected to each output of said one set of outputs, said one data line connected to each output of said one set of outputs is multiplexed by said sub-array multiplexing means to the bit line segments of a corresponding one of said bit lines, said one data line connected to each output of said one set of outputs is parallel to and adjacent to said corresponding one of said bit liens, said data lines include one data line connected to each output of said another set of outputs, said one data line connected to each output of said another set of outputs is multiplexed by said sub-array multiplexing means to the bit line segments of a corresponding group of a plurality of neighboring ones of said bit lines, and said one data line connected to each output of said another set of outputs is parallel to and adjacent to one bit line in said corresponding group of a plurality of neighboring ones of said bit lines.

2. The cache memory system as claimed in claim 1, wherein none of said data liens extend over any regions of said semiconductor substrate allocated to one of the sub-arrays of memory cells, and each of said data liens extends over regions of said semiconductor substrate allocated to said memory cells in a respective column of said memory cells in each of the sub-arrays of memory cells other than said one of said sub-arrays of memory cells.

3. The cache memory system as claimed in claim 1, wherein said data lines are formed in a metalization layer separate from and overlaying a metalization layer in which the bit lines are formed.

4. The cache memory system as claimed in claim 1, further comprising a translation buffer memory for translating one portion of a virtual address to provide said sub-array address, and wherein said row address is another portion of said virtual address that is not translated by said translation buffer memory and that exists before said translation buffer memory translates said one portion of said virtual address.

5. The cache memory system as claimed in claim 1, wherein said memory is a read/write memory, and said column multiplexing means and said sub-array multiplexing means are bidirectional.

6. The cache memory system as claimed in claim 1, wherein said sub-array multiplexing means comprises a row of read-write sense amplifiers associated with each sub-array, the row of read-write sense amplifiers being in parallel with the rows of memory cells in the sub-array.

7. The cache memory system as claimed in claim 6, wherein each data line is connected to one of said read-write sense amplifiers in each row of read/write sense amplifiers.

8. An integrated circuit cache memory system on a semiconductor substrate, said cache memory system having an array of rows and columns of memory cells, word lines extending along the rows of memory cells, bit lines extending along the columns of memory cells, and an address decoder decoding row addresses to assert select signals on addressed ones of said word lines, each memory cell including means for asserting a stored information signal on the bit line along the column of said each memory cell when said address decoder asserts a select signal on the word line along the row of said each memory cell, said cache memory system having one set of outputs from some of said bit lines and column multiplexing means responsive to a column address for multiplexing others of said bit lines to another set of outputs, wherein the improvement comprises

said array being physically subdivided into a multiplicity of sub-arrays of neighboring rows of memory cells, each bit line being discontinuous between the sub-arrays so that each bit line has a bit line segment extending along a column in each of the sub-arrays, and each of said memory cells in each column of each sub-array has a connection to the bit line segment extending along said each column of said each sub-array, and said memory system further including data lines for conveying information signals from said bit line segments to said outputs, said data lines extending over regions of said semiconductor substrate allocated to said memory cells without connections to said memory cells in the array, and said memory system further including sub-array multiplexing means responsive to a sub-array address for multiplexing information signals on said bit line segments of an addressed one of said sub-arrays to said data lines, wherein said data lines include one data line connected to each output of said one set of outputs, said one data line connected to each output of said one set of outputs is multiplexed by said sub-array multiplexing means to the bit line segments of a corresponding one of said bit liens, said one data line connected to each output of said one set of outputs is parallel to and adjacent to said corresponding one of said bit lines, said data lines include one data line connected to each output of said another set of outputs, said one data line connected to each output of said another set of outputs is multiplexed by said sub-array multiplexing means to the bit line segments of a corresponding group of a plurality of neighboring ones of said bit lines, and said one data line connected to each output of said another set of outputs is parallel to and adjacent to one bit line in said corresponding group of a plurality of neighboring ones of said bit lines, said memory is a read/write memory, said column multiplexing means and said sub-array multiplexing means are bidirectional, said sub-array multiplexing means comprises a row of read-write sense amplifiers being in parallel with the rows of memory cells in said each sub-array, and wherein each data line is connected to one of said read-write sense amplifiers in each row of read-write sense amplifiers, and said data lines are formed in a metalization layer separate from and overlaying a metalization layer in which the bit lines are formed.

9. The memory system as claimed in claim 8, further comprising a translation buffer memory for translating one portion of a virtual address to provide said sub-array address, and wherein said rows of memory cells are not selected by any translation of said virtual address by said translation buffer memory, and wherein said row address is provided by another portion of said virtual address that exists before said translation buffer memory translate said one portion of said virtual address.

10. An integrated circuit cache memory system on a semiconductor substrate, said cache memory system having an array of rows and columns of memory cells, word lines extending along the rows of memory cells, bit lines extending along the columns of memory cells, and an address decoder decoding row addresses to assert select signals on addressed ones of said word lines, each memory cell including means for asserting a stored information signal on the bit line along the column of said each memory cell when said address decoder asserts a select signal on the word line along the row of said each memory cell, said cache memory having one set of outputs from some of said bit lines, and column multiplexing means responsive to a column address for multiplexing others of said bit lines to another set of outputs, wherein the improvement comprises

said array being physically subdivided into a multiplicity of sub-arrays of neighboring rows of memory cells, each bit line being discontinuous between the sub-arrays so that each bit line has a bit line segment extending along a column in each of the sub-arrays, and each of said memory cells in each column of each sub-array has a connection to the bit line segment extending along said each column of said each sub-array, and said memory system further including data lines for conveying information signals from said bit line segments to said outputs, said data lines extending over regions of said semiconductor substrate allocated to said memory cells without connections to said memory cells in the array, and said memory system further including sub-array multiplexing means responsive to a sub-array address for multiplexing information signals on said bit line segments of an addressed one of said sub-arrays to said data lines, wherein said data lines include one data line connected to each output of said one set of outputs, said one data line connected to each output of said one set of outputs is multiplexed by said sub-array multiplexing means to the bit line segments of a corresponding one of said bit liens, said one data line connected to each output of said one set of outputs is parallel to and adjacent to said corresponding one of said bit lines, said data lines include one data line connected to each output of said another set of outputs, said one data line connected to each output of said another set of outputs is multiplexed by said sub-array multiplexing means to the bit line segments of a corresponding group of a plurality of neighboring ones of said bit lines, and said one data line connected to each output of said another set of outputs is parallel to and adjacent to one bit line in said corresponding group of a plurality of neighboring ones of said bit lines, said memory is a read/write memory, said column multiplexing means and said sub-array multiplexing means are bidirectional, said sub-array multiplexing means comprises a row of read-write sense amplifiers being in parallel with the rows of memory cells in said each sub-array, and wherein each data line is connected to one of said read-write sense amplifiers in each row of read-write sense amplifiers, and

further including a translation buffer memory for translating one portion of a virtual address to provide said sub-array address, said rows of memory cells not being selected by any translation of said virtual address by said translation buffer memory, and wherein said row address is provided by another portion of said virtual address that exists before said translation buffer memory translates said one portion of said virtual address.