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Semiconductor memory device having a boost circuit

  • US 5,253,204 A
  • Filed: 08/19/1991
  • Issued: 10/12/1993
  • Est. Priority Date: 08/20/1990
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device including an array of memory cell transistors connected to a plurality of word lines and bit lines, comprising:

  • a node to which a voltage boosted above a supply voltage is supplied;

    first means for producing a first voltage that is larger than said supply voltage;

    a MOS transistor connected between said first means and said node for selectively transferring electric charges from said first means to said node, said MOS transistor producing said voltage boosted above said supply voltage at said node;

    second means for supplying a second voltage larger than said supply voltage to a gate of said MOS transistor; and

    means for preventing said second voltage from rising above a predetermined voltage.

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