Semiconductor memory device having a boost circuit

• US 5,253,204 A
• Filed: 08/19/1991
• Issued: 10/12/1993
• Est. Priority Date: 08/20/1990
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Hatakeyama
• Inventors: Hatakeyama, Atsushi, Nakano, Masao
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/747,049
• Time in Patent Office: 785 Days
• Field of Search: 365/189.06, 365/230.06, 365/189.11, 365/203
• US Class Current: 365/189.06
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a word line selection circuit for selecting a word line, a bit line selection circuit for selecting a bit line, an input/output circuit for supplying data to be written to a selected memory cell via the selected bit line and for reading data from the selected memory cell via the selected bit line, a word line driver including a MOS transistor having a drain supplied with a supply voltage and a source connected to the word line selection circuit for supplying a word line voltage to the selected word line via the word line selection circuit, a word line boosting circuit connected to the drain of the MOS transistor for boosting the word line voltage via the MOS transistor, a boosting capacitor connected across the source and the gate of the MOS transistor, and a clamping circuit connected to the gate of said MOS transistor for clamping the voltage level at a predetermined level.

Claims

1. A semiconductor memory device including an array of memory cell transistors connected to a plurality of word lines and bit lines, comprising:

a node to which a voltage boosted above a supply voltage is supplied;

first means for producing a first voltage that is larger than said supply voltage;

a MOS transistor connected between said first means and said node for selectively transferring electric charges from said first means to said node, said MOS transistor producing said voltage boosted above said supply voltage at said node;

second means for supplying a second voltage larger than said supply voltage to a gate of said MOS transistor; and

means for preventing said second voltage from rising above a predetermined voltage.

2. A semiconductor memory device including an array of memory cell transistors connected to a plurality of word lines and bit lines, comprising:

a node to which a voltage boosted above a supply voltage is supplied;

first means for producing a first voltage that is larger than said supply voltage;

a MOS transistor connected between said first means and said node for selectively transferring electric charges from said first means to said node, said MOS transistor producing said voltage boosted above said supply voltage at said node;

second means for supplying a second voltage larger than said supply voltage to a gate of said MOS transistor;

means for preventing said second voltage from rising above a predetermined voltage; and

a word decoder for supplying a selection signal to a word line;

said first voltage at said node being supplied as a drive signal of said word decoder.

3. A semiconductor memory device including an array of memory cell transistors connected to a plurality of word lines and bit lines and a word decoder for selecting one of said plurality of word lines, comprising:

a node to which a voltage boosted above a supply voltage is supplied;

first means for producing a first voltage that is larger than said supply voltage;

a MOS transistor connected between said first means and said node for selectively transferring electric charges from said first means to said node, said MOS transistor producing said voltage boosted above said supply voltage at said node;

second means for supplying a second voltage larger than said supply voltage to a gate of said MOS transistor; and

means for preventing said second voltage from rising above a predetermined voltage;

said word decoder including said MOS transistor and said second means in correspondence to each of said word lines such that said node is connected to a corresponding word line;

said second means of producing said second voltage selectively in response to an address signal supplied to said word decoder.

4. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells for storing data, a plurality of word lines connected to the memory cells, and a plurality of bit lines connected to the memory cells;

word line selection means connected to each of the word lines and supplied with first address data specifying one of the word lines to which a selected memory cell is connected, for selecting the specified word line;

bit line selection means connected to each of the bit lines and supplied with second address data specifying one of the bit lines to which said selected memory cell is connected, for selecting the specified bit line;

input/output means connected to the bit line selection means for supplying data to be written into the selected memory cell to the selected bit line, and for reading data from the selected memory cell via the selected bit line;

word line drive means comprising a MOS transistor having a gate, a drain and a source, said source being connected to the word line selection means, said MOS transistor being supplied with an activation signal at the gate and producing a word line voltage at the source such that the word line voltage is supplied to the selected word line via the word line selection means;

word line boosting means connected to the drain of the MOS transistor for boosting the word line voltage via said MOS transistor, said word line boosting means including a boosting capacitor having a first end connected to the source of said MOS transistor and a second end connected to the gate of said MOS transistor for boosting a voltage level at the gate of the MOS transistor above said supply voltage in correspondence to the boosting of the word line voltage; and

clamping means connected to the gate of said MOS transistor for clamping the voltage level of the gate of the MOS transistor at a predetermined level.

5. A semiconductor memory device as claimed in claim 4 in which said clamping means comprises a plurality of MOS transistors connected in series between the gate of the MOS transistor of the word line drive means and the supply voltage, each of said MOS transistors of said clamping means having a gate and a drain connected with each other.

6. A semiconductor memory device as claimed in claim 4 in which said clamping means comprises a MOS capacitor connected between the gate of the MOS transistor of the word line drive means and the supply voltage.

7. A semiconductor memory device as claimed in claim 4 in which said boosting capacitor comprises a capacitance formed between the gate and the drain of the MOS transistor of the word line boosting means.

8. A semiconductor memory device as claimed in claim 4 in which said boosting means further comprises a second boosting capacitor having an end connected to the drain of the MOS transistor and a second end supplied with a boosting signal for boosting a voltage level of the drain of the MOS transistor above the supply voltage in response to the boosting signal.

9. A semiconductor memory device as claimed in claim 4 further comprising a precharge circuit connected to the drain of the MOS transistor of the word line drive means for supplying the supply voltage thereto.

10. A semiconductor memory device as claimed in claim 4 further comprising a drive circuit connected to the gate of the MOS transistor of the word line drive means for activating the same when supplying the word line voltage to the selected word line, said drive circuit releasing said gate of the MOS transistor of the word line drive means to a floating state when the boosting of the word line is started by the boosting means.

11. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells for storing data, a plurality of word lines connected to the memory cells, and a plurality of bit lines connected to the memory cells;

word line selection means connected to each of the word lines and supplied with first address data specifying one of the word lines to which a selected memory cell is connected, for selecting the specified word line;

bit line selection means connected to each of the bit lines and supplied with second address data specifying one of the bit lines to which said selected memory cell is connected, for selecting the specified bit line;

input/output means connected to the bit line selection means for supplying data to be written into the selected memory cell to the selected bit line, and for reading data from the selected memory cell via the selected bit line;

word line drive means for supplying a word line voltage to the selected word line via the word line selection means;

word line boosting means connected to the word line drive means for boosting the word line voltage;

said word line selection means comprising a plurality of MOS transistors provided in correspondence to the plurality of word lines, each of said MOS transistors having a gate, a drain connected to the word line drive means for receiving the word line voltage, and a source connected to the word line corresponding to the MOS transistor, said MOS transistor having a capacitance between the gate and the source; and

clamping means provided in correspondence to each of said plurality of MOS transistors electrically connected to the gate of said MOS transistor for clamping a voltage level of said gate at a predetermined level.

12. A semiconductor device comprising:

a node to which a voltage boosted above a supply voltage is supplied;

first means for producing a first voltage that is larger than said supply voltage;

a MOS transistor connected between said first means and said node for selectively transferring electric charges from said first means to said node, said MOS transistor producing said voltage boosted above said supply voltage at said node;

second means for supplying a second voltage larger than said supply voltage to a gate of said MOS transistor; and

means for preventing said second voltage from rising above a predetermined voltage.