Semiconductor memory device having dual ports

• US 5,253,207 A
• Filed: 11/18/1991
• Issued: 10/12/1993
• Est. Priority Date: 11/20/1990
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Shikatani, Junichi
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US07/793,968
• Time in Patent Office: 694 Days
• Field of Search: 365/189.04, 365/189.01, 365/189.03, 365/230.05, 365/233.5
• US Class Current: 365/189.04
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A semiconductor memory device in which dual ports are provided for selecting a specific memory cell from a memory cell matrix includes a driving state detection unit for detecting the state of driving word lines of the two ports and delivering a detection signal based on the detection, where one of the ports is in the writing state with regard to the memory cell, and a bit line short-circuiting unit responsive to the detection signal from the driving state detection unit for realizing a short-circuit between predetermined bit lines.

Claims

1. A semiconductor memory device in which dual ports are provided for selecting a specific memory cell from a memory cell matrix, and word lines and bit lines in the ports of the dual ports are driven independently for each port to write data into or read data from the memory cell, said device comprising:

a driving state detection means for detecting a state of driving word lines of the two ports and delivering a detection signal based on the detection, where one of the ports is in the writing state with regard to the memory cell; and

bit line short-circuiting means responsive to said detection signal from said driving state detection means for realizing a short-circuit between predetermined bit lines.

2. A semiconductor memory device in which dual ports are provided for selecting a specific memory cell from a memory cell matrix, and word lines and bit lines in the ports of the dual ports are driven independently for each port to write data into or read data from the memory cell, said device comprising:

a driving state detection means for detecting the state of driving word lines of the two ports and delivering a detection signal based on the detection, where one of the ports is in the writing state with regard to the memory cell; and

bit line short-circuiting means responsive to said detection signal from said driving state detection means for realizing a short-circuit between a bit line of one port and a bit line of the other port.

3. A semiconductor memory device in which dual ports are provided for selecting a specific memory cell from a memory cell matrix, and word lines and bit lines in the ports of the dual ports are driven independently for each port to write data into or read data from the memory cell, said device comprising:

a driving state detection means for detecting the state of driving word lines of the two ports and delivering a detection signal based on the detection, where one of the ports is in the writing state with regard to the memory cell; and

bit line short-circuiting means responsive to said detection signal from said driving stat detection means for realizing a short-circuit of a bit line pair of the port opposite to the writing side port.