High-performance memory controller with application-programmable optimization

• US 5,253,214 A
• Filed: 09/27/1991
• Issued: 10/12/1993
• Est. Priority Date: 09/27/1991
• Status: Expired due to Term

• Current Assignee: Eastman Kodak Company
• Original Assignee: Eastman Kodak Company
• Inventors: Herrmann, James F.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Kessell, Michael
• Application Number:
  US07/766,302
• Time in Patent Office: 746 Days
• Field of Search: 365/233, 365/203
• US Class Current: 365/233.14
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller (18) for controlling a multiplexed-address memory (14) includes a programmable timer (22) whose time-out period can be controlled by the memory-access device (12) to which the memory controller (18) provides memory access. During an idle period after a memory access, the controller'"'"'s memory operator (20) keeps the row-address-strobe signal asserted, and thereby permits page-mode addressing on the next cycle, until the counter (22) times out, at which point the memory operator (20) releases the row- address-strobe line and thereby initiates the pre-charge operation that is required before a row-address change. The memory access device (12) can thus change the time for which the row-address-strobe signal is kept asserted after a cycle to different values for different applications that it is running. The memory-access device (12) can thus optimize, on an application-specific basis, the compromise between the pre-charge penalties of page misses and the column-address-only benefits of page hits.

Claims

1. A memory controller, adapted to receive access signals from a memory-access device, for responding thereto by controlling a page-mode multiplexed-address memory adapted for reception of memory-address, row-address-strobe, and column-address-strobe signals, the memory keeping a row address latched therein in response to a first, hold state of the row-address-strobe signal and precharging in response to a second, precharge state of the row-address-strobe signal, the memory controller comprising:

A) a programmable timer responsive to a program signal to store a duration value set thereby and generate a timeout signal when the controller, has been idle, along with the row-address-strobe signal in the hold state, for a time interval the duration of which stored duration value represents; and

B) a memory operator connected to receive the timeout signal and being responsive to the access signals to access the memory by applying address, row-address-strobe, and column-address-strobe signals thereto, the memory operator keeping the row-address-strobe signal in the hold state during idle periods after an access until it receives the timeout signal and then switching the row-address-strobe signal to its precharge level.

2. A memory controller as defined in claim 1 wherein:

A) the access signals include address and accompanying data signals representing address and data values, respectively;

B) the programmable timer is associated with a predetermined timer address; and

C) the programmable timer stores as the duration values the values represented by data signals that accompany address signals representing the predetermined timer address, the programmable timer thereby treating the access signals that include such address signals as program signals.