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High-performance memory controller with application-programmable optimization

  • US 5,253,214 A
  • Filed: 09/27/1991
  • Issued: 10/12/1993
  • Est. Priority Date: 09/27/1991
  • Status: Expired due to Term
First Claim
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1. A memory controller, adapted to receive access signals from a memory-access device, for responding thereto by controlling a page-mode multiplexed-address memory adapted for reception of memory-address, row-address-strobe, and column-address-strobe signals, the memory keeping a row address latched therein in response to a first, hold state of the row-address-strobe signal and precharging in response to a second, precharge state of the row-address-strobe signal, the memory controller comprising:

  • A) a programmable timer responsive to a program signal to store a duration value set thereby and generate a timeout signal when the controller, has been idle, along with the row-address-strobe signal in the hold state, for a time interval the duration of which stored duration value represents; and

    B) a memory operator connected to receive the timeout signal and being responsive to the access signals to access the memory by applying address, row-address-strobe, and column-address-strobe signals thereto, the memory operator keeping the row-address-strobe signal in the hold state during idle periods after an access until it receives the timeout signal and then switching the row-address-strobe signal to its precharge level.

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