Control and maintenance subsystem network for use with a multiprocessor computer system

• US 5,253,359 A
• Filed: 06/11/1990
• Issued: 10/12/1993
• Est. Priority Date: 06/11/1990
• Status: Expired due to Term

• Current Assignee: Silicon Graphics International Corporation (Hewlett-Packard Enterprise Company)
• Original Assignee: Supercomputer Systems Limited Partnership
• Inventors: Rhea, Cris J., Beard, Douglas R., Spix, George A., Collier, Glen L., Throop, G. Joseph, Clounch, David L.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US07/535,901
• Time in Patent Office: 1,219 Days
• Field of Search: 395/800, 395/575, 395/200, 395/275, 395/325, 371/18
• US Class Current: 714/46
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component
• CPC Class Codes: G06F 11/2046 where the redundant components share persistent storage G06F11/2043 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/2736 using a dedicated service processor for test
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence
• CPC Class Codes: H04L 69/00 Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass networks security protocols H04L9/40; wireless communication networks H04W

Abstract

Methods and apparatus for a maintenance and control system for sensing and controlling the numerous sections of a highly parallel multiprocessor system. The control and maintenance system communicates with all processors, all peripheral systems, all user interfaces to the multiprocessor system, a system console, and the power and environmental control subsystems.

Claims

1. A control and maintenance subsystem for use with a shared memory multiprocessor computer system, comprising:

two or more computer processors tightly coupled to form said shared memory multiprocessor computer system including at least a first and second maintenance and control unit, each maintenance and control unit operably connected to one or more of said computer processors;

one or more peripheral devices connected to said computer processors, and including a third maintenance and control unit;

a maintenance and control network, connected to said first, second and third maintenance and control units and separate from any connections among said two or more computer processors that form said multiprocessor computer system, each maintenance and control unit including;

a processor means for performing a plurality of maintenance and control operations on one or more devices connected to said maintenance and control unit;

for each of said one or more devices, a scan path logic means for reading and writing scan path chains of information to and from one or more ports accessing internal logic in said device; and

an interface means for electronically interfacing said processor means with said scan path logic means for said one or more devices connected to said maintenance and control unit and with said scan path logic means for one or more devices connected to another of said maintenance and control units, such that the scan path logic means for each device is connected to at least two separate maintenance and control units;

a single maintenance console means for interfacing with an operator, wherein said first, second and third maintenance control units and said maintenance console means are all connected to said maintenance and control network to allow communication of maintenance and control information among said first, second and third maintenance control units and said maintenance console means,

wherein said internal logic in one or more of said devices is divided into multiple maintenance partitions, each maintenance partition being provided with a clock control circuit for controlling operation of a clock signal for said internal logic of said maintenance partition which is independent from said clock control circuit in any other of said maintenance partitions, such that said processor means can control the operation of said clock signal in each of said maintenance partitions independently from the operation of said clock signal in any other of said maintenance partitions.

2. The maintenance and control subsystem of claim 1 wherein said clock control circuit for each of said maintenance partitions comprises:

a fatal error circuit means for receiving a fatal error input signal from said internal logic of said maintenance partition and an allow fatal error signal from said maintenance control unit and providing a fatal error output signal;

a counter circuit means for providing a counted number of clock cycles as provided by said maintenance control unit when an enable counted clock mode signal is received from said maintenance control unit; and

an enable clock circuit means operably connected to said fatal error circuit means and said counter circuit means for enabling said clock signal in said maintenance partition in response to a free running clock signal or said counted clock mode signal provided by said maintenance control unit and the absence of said fatal error output signal.

3. A control and maintenance subsystem for use in a highly parallel supercomputer, comprising:

a plurality of computer processors physically organized into two or more clusters and connected in a highly parallel configuration;

a plurality of processor maintenance and control units, wherein each of said processor maintenance and control units is connected to and associated with a unique one of said clusters of computer processors and each maintenance and control unit includes;

a processor means for performing a plurality of maintenance and control operations on one or more devices connected to said maintenance and control unit;

for each of said one or more devices, a scan path logic means for reading and writing scan path chains of information to and from one or more ports accessing internal logic in said device; and

an interface means for electronically interfacing said processor means with said scan path logic means for said one or more devices connected to said maintenance and control unit and with said scan path logic means for one or more devices connected to another of said maintenance and control units, such that the scan path logic means for each device is connected to at least two separate maintenance and control units;

a peripheral device subsystem connected to said plurality of computer processors;

a peripheral maintenance and control unit connected to said peripheral device subsystem;

a power distribution means connected to said plurality of said processor means and said peripheral device subsystem for controlling power sequencing of said processor means and said peripheral device subsystem;

a power maintenance control unit connected to said power distribution means;

a maintenance and control network, connected to said plurality of processor maintenance and control units, said peripheral maintenance and control unit and said power maintenance and control unit and separate from any connections among said plurality of computer processors that form said two or more clusters of said supercomputer system;

a system console means for interfacing with an operator, wherein said processor, peripheral, and power maintenance control units and said system console means are all connected together to said maintenance and control network to allow communication of maintenance and control information between said processor, peripheral, and power maintenance control units and said system console means,

wherein said internal logic in one or more of said devices is divided into multiple maintenance partitions, each maintenance partition being provided with a clock control circuit for controlling operation of a clock signal for said internal logic of said maintenance partition which is independent from said clock control circuit in any other of said maintenance partitions, such that said processor means can control the operation of said clock signal in each of said maintenance partitions independently from the operation of said clock signal in any other of said maintenance partitions.

4. The maintenance and control subsystem of claim 3 wherein said clock control circuit for each of said maintenance partitions comprises:

a fatal error circuit means for receiving a fatal error input signal from said internal logic of said maintenance partition and an allow fatal error signal from said maintenance control unit and providing a fatal error output signal;

a counter circuit means for providing a counted number of clock cycles as provided by said maintenance control unit when an enable counted clock mode signal is received from said maintenance control unit; and

an enable clock circuit means operably connected to said fatal error circuit means and said counter circuit means for enabling said clock signal in said maintenance partition in response to a free running clock signal or said counted clock mode signal provided by said maintenance control unit and the absence of said fatal error output signal.