Ferroelectric capacitor test structure for chip die
First Claim
1. In a semiconductor wafer of the type having a plurality of circuit die, and at least some of the die having a ferroelectric component, a method of incorporating a test structure in the semiconductor wafer, comprising the steps of:
- fabricating at least one ferroelectric test structure into each said die having ferroelectric component so that the test structure undergoes substantially the same processing environment as does functional circuitry of the die;
fabricating said ferroelectric test structure as a two-terminal device in series with a transistor switch for switchably connecting the ferroelectric component between bond pads; and
connecting the ferroelectric test structure so that each terminal of the ferroelectric test structure is coupled to a different bond pad of the respective die for providing electrical access to the test structure by way of said bond pads and so that analog tests can be conducted thereon and analog signals resulting from said tests can be obtained from at least one of the bond pads.
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Accused Products
Abstract
A test structure integrated into substantially each circuit die formed on a wafer. The test structure includes a ferroelectric component connected to bond pads of the die so that analog tests can be conducted thereon, and the results of the tests utilized to extrapolate aging and fatigue characteristics of other ferroelectric components in the functional circuits of the die. The ferroelectric test structure can be connected directly to die bond pads, or switchably connected thereto by decoding circuits which share bond pads employed by the other functional circuits of the die.
65 Citations
27 Claims
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1. In a semiconductor wafer of the type having a plurality of circuit die, and at least some of the die having a ferroelectric component, a method of incorporating a test structure in the semiconductor wafer, comprising the steps of:
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fabricating at least one ferroelectric test structure into each said die having ferroelectric component so that the test structure undergoes substantially the same processing environment as does functional circuitry of the die; fabricating said ferroelectric test structure as a two-terminal device in series with a transistor switch for switchably connecting the ferroelectric component between bond pads; and connecting the ferroelectric test structure so that each terminal of the ferroelectric test structure is coupled to a different bond pad of the respective die for providing electrical access to the test structure by way of said bond pads and so that analog tests can be conducted thereon and analog signals resulting from said tests can be obtained from at least one of the bond pads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for fabricating a test structure into a circuit die, comprising the steps of:
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fabricating in the die functional circuits embodying at least one ferroelectric component; fabricating bond pads on said die, at least some pads of which are employed for accessing the functional circuitry of the die; fabricating a test structure on the die including a ferroelectric component in series with a transistor, said ferroelectric component fabricated by substantially the same steps as utilized in fabricating the ferroelectric components of the functional circuitry; and connecting the ferroelectric test structure so that electrical access thereto can be had to at least one terminal of the ferroelectric component via a bond pad such that analog tests can be conducted thereon and analog signals from the ferroelectric component can be obtained via the bond pad to which the ferroelectric component is connected. - View Dependent Claims (12, 13, 14)
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15. A circuit die, comprising:
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a ferroelectric memory having a plurality of memory cells, each cell having at least one ferroelectric capacitor formed on a semiconductor material of said die, said ferroelectric memory storing data and defining a functional circuit, and being connected to a supply voltage; a plurality of bond pads connected to the functional circuit for providing electrical access thereto; a test structure having a ferroelectric component formed on said die, said test structure ferroelectric component undergoes substantially the same processing steps as utilized in fabricating the functional circuit ferroelectric memory cells; and said test structure being connected so that AC signals of amplitude equal to or less than said supply voltage can be applied to the bond pads and to the test structure, and said test structure is interconnected with respect to said ferroelectric memory so that analog tests can be conducted on said test structure without accessing the ferroelectric memory, and analog signals can be obtained from the test structures via ones of said bond pads. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A test array formed on a semiconductor wafer, comprising:
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an array of ferroelectric test structures, each test structure including a ferroelectric capacitor; at least one bit line for coupling signals to said test structures; an access transistor associated with each said test structure of independently connecting a respective ferroelectric capacitor to said bit line; and an input structure to said bit line for carrying analog signals ranging in amplitude from about a supply voltage to about a ground reference voltage to said test structures for subjecting the test structures to different amplitudes of said analog signals. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification