Probe card system

• US 5,254,939 A
• Filed: 03/20/1992
• Issued: 10/19/1993
• Est. Priority Date: 03/20/1992
• Status: Expired due to Fees

• Current Assignee: Xandex, Inc.
• Original Assignee: Xandex, Inc.
• Inventors: Phillips, Brian P., Anderson, James C., Honek, Charles
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/855,763
• Time in Patent Office: 578 Days
• Field of Search: 324/158 P, 324/158 F, 324/158 R, 324/73.1, 439/482, 414/222, 414/225, 414/749, 198/573
• US Class Current: 324/754.07
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A semiconductor wafer probe test interface system (2) and method of operating the system. The wafer probe system includes a plurality of cassettes (302) adapted to hold wafer probe test cards (304). The cassettes are loaded into position for testing of semiconductor wafers with a transport assembly system (6). A memory device (316) on the cassette is used to store data regarding usage of the card such as number of wafer touchdowns. A smart controller (220) has the capability to "talk" to the prober and tester.

Claims

1. A wafer test system comprising:

a) a plurality of cassettes, each of said cassettes comprising a wafer probe card and memory means, said memory means adapted to store operational data regarding said wafer probe card; and

b) loading means for removing and inserting said cassettes into said test system.

2. A wafer test system as recited in claim 1 wherein said operational data comprises a number of probe touchdowns.

3. A wafer test system as recited in claim 1 wherein said memory means is a serial memory device having a single data input contact.

4. A wafer test system as recited in claim 3 further comprising a wafer prober, and wherein said loading means further comprises a plurality of stepper motors, said stepper motors engaging said cassettes to drive aid cassettes into said wafer prober.

5. A wafer test system as recited in claim 3 further comprising a wafer prober and a detector for determining when said cassette is fully inserted into said wafer prober.

6. A wafer test system as recited in claim 1 wherein said wafer probe cards are removable from said cassettes.

7. A wafer test system as recited in claim 1 wherein said wafer probe cards comprise delicate probe tips, said probe tips biased away from an exterior of said cassette, said probe tips moved outwards of said exterior of said cassette upon reaching a working position in a wafer prober.

8. A wafer test system as recited in claim 7 wherein said probe card is biased in said cassette with springs.

9. A wafer test system as recited in claim 1 wherein said memory is adapted to store the information selected from a group of Touchdowns, Serial number, Date of last maintenance, Date of manufacture, Failure nature of probes, Location of failed probes, operator'"'"'s I.D., Scheduled maintenance date, Scheduled maintenance touchdowns, and Previous radial orientation.

10. A wafer test system as recited in claim 1 further comprising a transport assembly for loading said cassettes into said system.

11. A wafer test system as recited in claim 10 wherein said transport assembly comprises tracks for guiding said cassettes into said system, and stepper motors for driving said cassettes into a selected position.

12. A wafer test system as recited in claim 1 further comprising a memory data transfer means in said wafer test system for both writing to and reading from said memory.

13. A wafer test system as recited in claim 1 further comprising a display, said wafer test system adapted to read said memory and display a number of touchdowns on said display when said cassettes are loaded into said system.

14. A wafer test system as recited in claim 13 wherein said system is adapted to display maintenance history information regarding said cassettes.

15. A wafer test system as recited in claim 1 wherein said memory is adapted to interface with a standard RS-232 data bus.

16. A wafer test system as recited in claim 1 wherein said cassettes comprise a real time clock for time stamping usage and maintenance durations.

17. A wafer test system as recited in claim 1 further comprising a magazine for holding a plurality of said cassettes, and means for loading a selected one of said cassettes into said system from said magazine.

18. A wafer test system as recited in claim 17 wherein said selected one of said cassettes is selected based on input regarding a wafer product from a user interface.

19. A semiconductor wafer probe card cassette comprising:

a body;

a probe card mounted in said body, said probe card comprising a plurality of probes for transmitting electrical signals to a semiconductor wafer; and

a semiconductor memory mounted on said cassette, said semiconductor memory storing operational data regarding said probe card.

20. A semiconductor wafer probe card cassette as recited in claim 19 wherein said semiconductor memory is mounted on said body.

21. A semiconductor wafer probe card cassette as recited in claim 19 wherein said semiconductor memory is mounted on said probe card.

22. A semiconductor wafer probe card cassette as recited in claim 19 wherein said semiconductor memory comprises a single data input/output terminal, said semiconductor memory adapted to input and output data in a serial manner.

23. A semiconductor wafer probe card cassette as recited in claim 19 wherein said probe card is movably mounted in said body whereby said probe card can move from a first position to a second position, said probe card comprising probe pins extending from said probe card, said probe pins extending outside of said body in said first position, but not extending from said body in said second position.

24. A system for testing semiconductor wafers comprising:

a) a plurality of cassettes, each of said cassettes comprising a wafer probe card and a semiconductor memory, said semiconductor memory adapted to serially input and output a number of touchdowns of said wafer probe card to said semiconductor wafers; and

b) a transport assembly for moving a selected one of said cassettes into a wafer prober, said transport assembly comprising a single data input pin for serially reading a said number of touchdowns from said semiconductor memory when said cassettes are inserted into said wafer prober, and for inputting an updated number of touchdowns to said memory when said cassettes are removed from said wafer prober.

25. A system as recited in claim 24 wherein said wafer probe cards are biased in said cassettes such that probe tips on said probe card are normally biased so as to not extend outside of said cassettes.

26. A system as recited in claim 25 wherein said system further comprises a slidable piston for forcing said wafer probe card in a direction such that said probe tips extend from said cassettes for testing, and wherein said system is programmed to prevent insertion of said cassettes when said piston is in a position for forcing said wafer probe card such that said probe tips extend from said cassettes.

27. A system as recited in claim 24 further comprising a menu driven user interface, said user interface advising a user for how to insert said cassettes into said system.

28. A system as recited in claim 24 further comprising a controller means, said controller means being programmed to reject said cassettes if said number of touchdowns exceeds a selected value.

29. A system as recited in claim 24 wherein said semiconductor memory is adapted to store a previous radial orientation of said probe card, said previous radial orientation being used for proper alignment of said probe card upon insertion into said system.