DMD display system controller

• US 5,254,980 A
• Filed: 09/06/1991
• Issued: 10/19/1993
• Est. Priority Date: 09/06/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Asahara, Masaho, Urbanus, Paul M., Hendrix, Henry D.
• Primary Examiner(s): HJERPE, RICHARD A
• Application Number:
  US07/756,007
• Time in Patent Office: 774 Days
• Field of Search: 340/783, 340/784, 340/785, 340/786, 340/787, 340/788, 358/188, 358/160, 358/230, 358/240, 358/241
• US Class Current: 345/84
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2340/0492 Change of orientation of the displayed image, e.g. upside-down, mirrored
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833

Abstract

A method and structure for providing system control to a spatial light modulator display are disclosed. The control functions are divided into smaller, easier to implement control blocks and coordination between them is provided. The smaller blocks are a memory controller, a modulator controller and a formatter controller.

Claims

1. A method for controlling a spatial light modulator display system comprising:

a. dividing the display system control, and data transfer functions into a data formatter controller to supply address and control signals to at least one data formatter, a memory controller to control at least one video memory, and a modulator controller to supply address and modulator control signals to at least one spatial light modulator; and

b. generating signals between said controllers to coordinate the addressing, reading, writing, and transferring of data between a data formatter, a memory, and a modulator, such that said transfers are done to provide said data and said modulator control signals to said modulator.

2. The method of claim 1 wherein said dividing step further comprises dividing said formatter controller into an input controller to govern the write address of said formatter, an output controller to govern the read address of said data formatter and a address multiplexer to multiplex said read and write addresses from the input and output controllers.

3. The method of claim 1 wherein said dividing step further comprises;

a. dividing said memory controller into;

i. a line counter to track the current active line number;

ii. a requester to initiate refresh and transfer operations;

iii. a state machine to coordinate the operations of said memory controller;

iv. a transfer controller to coordinate said reading and writing of data to and from said memory;

v. a multiplexer/demultiplexer to select mapping table addresses based on current operational state;

vi. a first-in-first-out buffer initializer to control an optional first-in-first-out buffer memory; and

vii. a dynamic memory allocator to control writing data to, reading data from, and refreshing of said video memory;

b. generating signals between said line counter, said requester, said state machine, said transfer controller, said multiplexer/demultiplexer, said buffer initializer, and said dynamic memory allocator to coordinate the reading and writing of data to, and refreshing of, a video memory.

4. The method of claim 1 wherein said dividing step further comprises;

a. dividing said modulator controller into;

i. a sequence memory to control the sequence of events;

ii. a state machine to control the state of said modulator controller;

iii. a write and clear function to control writing to and clearing of said modulator;

iv. a reset controller to coordinate the reset of said modulator;

v. an address controller to determine the video memory address from which data is read;

vi. and an analog multiplexer to select the required modulator bias voltage;

b. generating signals between said memory, said state machine, said write and clear function, said reset controller, said address controller, and said analog multiplexer to coordinate the transfer of data to, and the display of data upon, a spatial light modulator.

5. The method of claim 1 wherein said dividing step further comprises dividing said memory controller into a state controller circuit to coordinate the operation of the memory controller and to track display line number;

and an address generation circuit which receives control and line number signals from the state controller circuit and controls reading, writing, and refreshing of the video memory and coordinates the operations of the memory controller with the formatter controller and modulator controller.

6. The method of claim 1 wherein said dividing step further comprises dividing said modulator controller into a state controller circuit to coordinate the operation of the modulator controller and an address and control circuit which receives control signals from the state controller and controls writing to and biasing of the spatial light modulator.

7. A system controller for a spatial light modulator display system comprising:

a. a modulator controller to control at least one spatial light modulator;

b. a memory controller to control at least one video memory;

c. a formatter controller to supply address and control signals to at least one data formatter;

d. signals between said modulator controller and said memory controller, between said modulator controller and said formatter controller, and between said memory controller and said formatter controller, to coordinate the operations of at least one formatter, at least one memory, and at least one modulator and to coordinate the transfers of data between said formatter, said memory, and said modulator, said operations and transfers performed to accurately represent a visual image upon said modulator.

8. The controller of claim 7 wherein said formatter controller further comprises an input controller to govern the write address of said data formatter, an output controller to govern the read address of said data formatter, and a address multiplexer to multiplex said read and write addresses.

9. The controller of claim 7 wherein said memory controller further comprises

a. a line counter to track the current active line number;

b. a requester to initiate refresh and transfer operations;

c. a state machine to coordinate the operations of said memory controller;

d. a transfer controller to coordinate read and write operations;

e. a multiplexer/demultiplexer to select mapping table addresses based on current operational state;

f. a first-in-first-out buffer initializer to control an optional first-in-first-out buffer memory;

g. a dynamic memory allocator to control writing data to, reading data from, and refreshing of said video memory; and

h. signals between said line counter, said requester, said state machine, said transfer controller, said multiplexer/demultiplexer, said buffer initializer, and said dynamic memory allocator to coordinate the reading and writing of data to, and refreshing of, at least one video memory.

10. The controller of claim 7 wherein said modulator controller further comprises;

a. a sequence memory to control the sequence of events;

b. a state machine to control the state of said modulator controller;

c. a write and clear function to control writing to and clearing of said modulator;

d. a reset controller to coordinate the reset of said modulator;

e. an address controller to determine the video memory address from which data is read;

f. an analog multiplexer to select the required modulator bias voltage; and

g. signals between said memory, said state machine, said write and clear function, said reset controller, said address controller, and said analog multiplexer to coordinate the transfer of data to, and the display of data upon, at least one spatial light modulator.

11. The controller of claim 7 wherein said memory controller further comprises a state controller circuit to coordinate the operation of the memory controller and to track display line number;

and an address generation circuit which receives control and line number signals from the state controller circuit and controls reading, writing, and refreshing of the video memory and coordinates the operations of the memory controller with the formatter controller and modulator controller.

12. The controller of claim 7 wherein said modulator controller further comprises a state controller circuit to coordinate the operation of the modulator controller and an address and control circuit which receives control signals from the state controller and controls writing to and biasing of the spatial light modulator.

13. The system controller of claim 7 wherein said memory controller also provides circuitry to allow reversing the display of the video data from top to bottom of the spatial light modulator and independent circuitry to allow reversing the display of the video data from left to right of the spatial light modulator.

14. The system controller of claim 7 wherein said system controller also provides circuitry to synchronize the display system to an external color wheel.