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High capacity submicro-winchester fixed disk drive

  • US 5,255,136 A
  • Filed: 06/04/1991
  • Issued: 10/19/1993
  • Est. Priority Date: 08/17/1990
  • Status: Expired due to Term
First Claim
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1. A Winchester disk drive data storage subsystem for connecting with a host computing system, the data storage subsystem including a head and disk assembly defining a disk spindle, a brushless DC spindle motor formed at said spindle for rotating a disk hub at a constant angular velocity, at least one rotating disk mounted to said hub and having two data storage surfaces defining a plurality of concentric data storage track locations having a track density of at least approximately 1700 tracks per inch, a data transducer head for each surface, the heads being radially positionable among the track locations, a mass balanced rotary voice coil actuated head positioning system for moving the data transducer heads between track locations during track seeking and settling and for maintaining a selected one of the data transducer heads in alignment with centerline of a track during track following operations during which data blocks are written to or read from the track being followed, the storage surfaces defining a series of radially extensive servo sectors embedded within circumferential zones of data tracks, the sectors being recorded at a constant data transfer rate and each sector including servo information comprising a track number value and a plurality of radially offset and circumferentially staggered servo bursts, each zone having a data transfer rate adapted to disk radius, and read preamplifier, write driver, head select integrated circuit means connected for selecting each said data transducer head, for amplifying analog signals read from a said data storage surface, and for amplifying signals to be written to said surface, the disk drive subsystem further comprising subsystem electronics mounted on a circuit board and including:

  • read channel means connected to said read preamplifier, write driver and head select integrated circuit means for processing said analog signals into digital signal transitions, and including pulse detector means for detecting said analog signals, phase locked loop means for generating a digital read data clock synchronized detected analog signals, and frequency synthesizer means for generating frequency signals for the phase locked loop means in relation to the data transfer rate of each data zone,servo processing means connected to said read channel means for locating and processing said servo information located within each said servo sector into head position digital values,data block sequencer means connected to said read channel means for locating and assembling data blocks from a serial data stream read from, and for forming and sending a serial data stream to, the data storage surfaces and for handling data block transfers between the disk storage surfaces and a buffer memory means,buffer memory control means for handling transfers between the buffer memory means and a bus level interface means,the bus level interface means for transferring data blocks and control values between the host computing system and the subsystem via a bus level interface structure,the buffer memory means connected to said data block sequencer means and to said bus level interface means and controlled by said buffer memory control means for temporarily storing blocks of data passing between the subsystem and the host computing system, andprogrammed digital controller means connected to said read channel means, said servo processing means, said data block sequencer means said buffer memory control means and said bus level interface means, and including servo supervision routine means for supervising operations of the servo processing means by generating and applying digital head position correction values to the head positioning system from said head position digital values generated by said servo processing means, and including data block transfer supervision routine means for supervising operations of said data block sequencer means, said buffer memory control means and said bus level interface means.

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