Method for manufacturing a semiconductor device using a circuit transfer film

• US 5,256,562 A
• Filed: 11/04/1992
• Issued: 10/26/1993
• Est. Priority Date: 12/31/1990
• Status: Expired due to Term

• Current Assignee: Kopin Corporation
• Original Assignee: Kopin Corporation
• Inventors: Vu, Duy-Phach, Dingle, Jason E., Dingle, Brenda D., Cheong, Ngwe
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/970,675
• Time in Patent Office: 356 Days
• Field of Search: 437/205, 437/208, 437/86, 437/966, 437/974, 156/DIG. 88
• US Class Current: 438/28
• CPC Class Codes: A61B 3/113 for determining or recording eye movement
• CPC Class Codes: G02B 2027/0132 comprising binocular systems
• CPC Class Codes: G02B 2027/0138 comprising image capture systems, e.g. camera
• CPC Class Codes: G02B 2027/0187 slaved to motion of at least a part of the body of the user, e.g. head, eye
• CPC Class Codes: G02B 2027/0198 System for aligning or maintaining alignment of an image in a predetermined direction
• CPC Class Codes: G02B 27/0093 with means for monitoring data relating to the user, e.g. head-tracking, eye-tracking
• CPC Class Codes: G02B 27/0172 characterised by optical features
• CPC Class Codes: G02B 5/30 Polarising elements light-modulating devices with active elements G02F1/00
• CPC Class Codes: G02F 1/13336 Combining plural substrates to produce large-area displays, e.g. tiled displays
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13613 the semiconductor element being formed on a first substrate and thereafter transferred to the final cell substrate
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 2202/105 single crystal Si
• CPC Class Codes: G09G 2300/023 Display panel composed of stacked panels
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2340/0464 Positioning
• CPC Class Codes: G09G 2370/042 : for monitor identification
• CPC Class Codes: G09G 3/30 : using electroluminescent panels
• CPC Class Codes: G09G 3/32 : semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/36 : using liquid crystals
• CPC Class Codes: G09G 3/3607 : for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 : Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 : using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 21/8221 : Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2221/68359 : used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 : used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0756 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/10 : the devices having separate containers
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 : the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01065 : Terbium [Tb]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01S 5/0217 : Removal of the substrate
• CPC Class Codes: H01S 5/423 : having a vertical cavity
• CPC Class Codes: H04N 5/70 : Circuit details for electroluminescent devices
• CPC Class Codes: H04N 5/7441 : the modulator being an array of liquid crystal cells
• CPC Class Codes: H04N 5/7491 : of head mounted projectors
• CPC Class Codes: H04N 9/3141 : Constructional details thereof details not peculiar to the presence of an electronic spatial light modulator G03B21/14
• CPC Class Codes: H05B 33/12 : Light sources with substantially two-dimensional radiating surfaces

Abstract

The invention relates to the formation of arrays of thin film transistors (TFT'"'"'s) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body.

Claims

1. The process of forming electronic circuitry on a common body comprising the steps of:

a) forming a plurality of electronic circuits in a semiconductor film formed on a substrate;

b) dividing the substrate into a plurality of tiles;

c) transferring said tiles to a common body;

d) registering the tiles on said common body;

e) adhering said tiles to the common body;

f) removing the substrates tiles, leaving the circuits on the body; and

g) simultaneously forming circuit elements on said circuits so that each such element is aligned with each other element.

2. The process of claim 1 wherein the circuits are transistors and the elements are electrodes.

3. The process of claim 2 wherein the transistors are field effect transistors having source and drain regions extending in a plane and formed on opposite sides of a gate region and opaque shields formed on opposite sides of said plane.

4. The process of claim 1 wherein the circuits are formed in recrystallized polysilicon formed over a buried insulator and wherein the recrystallized polysilicon forms a essentially single crystal layer.

5. The process of claim 2 wherein the electrodes are formed of transparent conductive material.

6. The process of claim 3 including the step of covering transistors on two sides of the film by opaque material.

7. The process of claim 1 wherein the electronic circuits comprise thin film transistor circuits and driver circuits.

8. The process of claim 6 wherein the tiles are adhered using an ultra-violet light curing adhesive.

9. The process of claim 5 wherein the electrodes are formed of indium tin oxide.

10. The process of claim 7 wherein the tiles are divided using a process from the group comprising:

sawing, cleaving or etching.

11. The process of forming transistors and pixel electrodes for an active matrix liquid display comprising the steps of:

a) forming a plurality of transistors in a first semiconductor film formed on a first substrate;

b) dividing the substrate into circuit tiles and transferring said tiles to a common body;

c) removing the substrates from the tiles leaving the transistors on the body;

d) forming electrodes on the tiles adjacent the transistors.

12. The process of claim 11 wherein the film is formed of silicon material from the group comprising amorphous Si, polysilicon or single crystal silicon.

13. The process of claim 11 wherein the electrodes are formed of indium tin oxide.

14. The process of claim 11 wherein the transistors are covered by opaque material on sides opposite the plane of the film.

15. The process of claim 11 including an intermediate step in which the tiles are transferred to a transfer body where the substrates are removed before transfer of the tiles to the common body.

16. The process of claim 14 wherein the transistors have source, drain and body regions and wherein the opaque material is electrically conductive and is used to contact one or more of said regions to minimize stray capacitance effects.