Integral semiconductor wafer map recording

• US 5,256,578 A
• Filed: 12/23/1991
• Issued: 10/26/1993
• Est. Priority Date: 12/23/1991
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Corley, Dean, Littlebury, Hugh W.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US07/812,344
• Time in Patent Office: 673 Days
• Field of Search: 437/8, 437/7, 324/158 R, 324/158 T, 364/481, 364/491
• US Class Current: 438/17
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54466 Located in a dummy or reference die
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/94 Laser ablative material removal

Abstract

A method for integral semiconductor wafer map recording which comprises a semiconductor wafer (11) having a plurality of individual die (12, 13) thereon. Testing each of the individual die (12). Summarizing the results of the testing in a wafer map. Recording the wafer map on the semiconductor wafer (11) by laser scribing a binary code (19) within inactive die (13).

Claims

1. A method for integral semiconductor wafer map recording, comprising:

providing a semiconductor wafer;

fabricating a plurality of active die and a plurality of inactive die on a surface of the semiconductor wafer;

testing the active die;

summarizing the results of the testing in a wafer map;

compressing the wafer map to produce a binary code; and

recording the binary code by laser scribing within at least one of the inactive die.

2. The method for integral semiconductor wafer map recording of claim 1 further comprising:

categorizing each die based on the testing; and

summarizing the results of the categorizing in the wafer map.

3. The method for integral semiconductor wafer map recording of claim 1 wherein the inactive die comprise a plurality of process test patterns.

4. The method for integral semiconductor wafer map recording of claim 1 wherein the inactive die comprise a plurality of incomplete die around the periphery of the semiconductor wafer.

5. The method for integral semiconductor wafer map recording of claim 1 further comprising:

further recording a plurality of redundant copies of the binary code within a plurality of locations having inactive die.

6. The method for integral semiconductor wafer map recording of claim 1 further comprising:

reading the binary code from the inactive die by mechanical means.

7. The method for integral semiconductor wafer map recording of claim 1 further comprising:

encrypting the wafer map to produce an encrypted binary code; and

recording the encrypted binary code by laser scribing within at least one of the inactive die.

8. A method for integral semiconductor wafer map recording, comprising:

providing a semiconductor wafer;

fabricating a plurality of active die on the semiconductor wafer;

additionally fabricating a plurality of test patterns on the semiconductor wafer;

testing each of the active die;

categorizing each die based on the testing results;

summarizing the results of the categorization in a wafer map;

compressing the wafer map to produce a binary code;

recording the binary code by computer controlled laser scribing of a machine readable binary code within one of the test patterns;

further recording a plurality of redundant copies of the binary code within a plurality of test patterns which are positioned at different locations on the semiconductor wafer; and

reading the binary code from the test patterns by means of video and computer equipment.