Mask surrogate semiconductor process with polysilicon gate protection

• US 5,256,583 A
• Filed: 01/07/1992
• Issued: 10/26/1993
• Est. Priority Date: 03/21/1986
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Hollinger, Theodore G.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/817,867
• Time in Patent Office: 658 Days
• Field of Search: 437/29, 437/40, 437/41, 437/203, 437/187, 437/192, 437/194, 437/200, 437/245
• US Class Current: 438/268
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O₂ -SF₆ plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

Claims

1. A method, employing no more than one independent mask to form a mask-surrogate pattern definer, of producing a field-effect power MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, the method comprising:

forming a dopant protective layer over the gate oxide layer;

masking and patterning the dopant protective layer to form a mask-surrogate pattern-definer having a defined outline characteristic so that the pattern-definer protects an underlying gate oxide region and a first portion of the upper surface of the substrate;

selectively removing a portion of the dopant protective layer and of the oxide layer to expose a second portion of the upper surface of the substrate within a region defined by the defined outline characteristic;

performing a first doping step to introduce first dopant into said exposed second upper surface portion of the substrate so as to form a first region of a first conductivity type, defining a MOS body region, said first region extending to an extent under a peripheral edge of the protective layer;

performing a second doping step to introduce second dopant into said exposed second upper surface portion so as to form a second region of a second conductivity type, opposite the first conductivity type, defining a MOS source region;

said second MOS region being wholly contained in said first MOS region and not extending to said extent along the upper surface of the substrate, thereby to define a MOS channel beneath said gate oxide region;

the dopant protective layer including a dopant opaque polysilicon layer of a sufficient thickness to prevent the introduced dopants from penetrating the underlying gate oxide region, the polysilicon layer having an exposed upper surface;

reducing the thickness of the polysilicon layer; and

depositing a conductive material layer to form a gate conductive layer over the gate oxide region without a second masking step.

2. A method according to claim 1, wherein the second region of said second conductivity type is formed to extend a lateral distance under the peripheral edge of the protective layer that is 60%-80% of a depth of the first region from the upper surface of the substrate.

3. A method according to claim 1 including etching the polysilicon layer by an etchant that etches silicon preferentially to silicon dioxide so that the polysilicon layer is reduced in thickness without a second masking step.

4. A method according to claim 1 including, after the first and second doping steps, forming a trench in the exposed upper surface portion of the substrate, the trench being formed to a trench depth greater than the depth of the second region but less than the depth of the first region, and formed to a width less that the width of the second region such that separated regions of the second conductivity type are provided at sidewalls of the trench, the separated regions constituting source regions of the MOS semiconductor device.

5. A method according to claim 4, in which the step of depositing a conductive material layer is performed after forming the trench, the conductive material layer having a first portion in the trench in contact with the separated source regions, as a source conductive layer, and a second portion on the gate oxide region, as the gate conductive layer, so as to provide electrical conduction to the source and body regions and to form the gate conductive layer of the MOS semiconductor device.

6. A method according to claim 5, wherein the conductive layer is deposited such that said first portion, when deposited, is separated vertically from said second portion, the first and second portions being deposited at the same time.

7. A method according to claim 4 in which the step of forming the trench includes reducing the thickness of the polysilicon layer.

8. A method according to claim 4 in which the second doping step includes ion implanting a dopant into the exposed portion of the substrate prior to forming the trench so that the trench divides the doped substrate portion into separate source regions extending along each trench sidewall.

9. A method according to claim 4 in which the trench sidewalls are formed to extend laterally towards one another within the trench so that a portion of the silicon substrate containing the source regions of said second conductivity type is exposed along the trench sidewalls.

10. A method according to claim 9 in which the sidewalls are undercut beneath the gate oxide region.