Audit and pricing system for coin-operated games
First Claim
Patent Images
1. A coin operated, stand alone amusement game comprising:
- a) a microprocessor for controlling the game responsive to player inputs and game rules;
b) read only memory means in which the game rules are stored;
c) a collector clearable memory means in which selected game play statistics are stored for readout by a collector to determine the revenue generated by the game and its popularity with players;
d) a secured memory means which cannot be cleared by the collector;
e) resettable clock means for generating the current time and date;
f) means for storing in said secured memory means the time and date;
(i) when the clock means was last set, and (ii) each time the clearable memory means is cleared;
g) bus means for electrically interconnecting the microprocessor to the various memory means and said resettable clock;
whereby unauthorized alteration of the statistics stored in said clearable memory means is detected.
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Abstract
An audit system for recording the activation of coin-operated electronic equipment and the amounts of money collected employing a real-time clock to time stamp information recorded in non-volatile or battery powered memory, such as total collections, number of games played, etc. The system also allows selective pricing based on a time of day schedule.
319 Citations
3 Claims
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1. A coin operated, stand alone amusement game comprising:
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a) a microprocessor for controlling the game responsive to player inputs and game rules; b) read only memory means in which the game rules are stored; c) a collector clearable memory means in which selected game play statistics are stored for readout by a collector to determine the revenue generated by the game and its popularity with players; d) a secured memory means which cannot be cleared by the collector; e) resettable clock means for generating the current time and date; f) means for storing in said secured memory means the time and date;
(i) when the clock means was last set, and (ii) each time the clearable memory means is cleared;g) bus means for electrically interconnecting the microprocessor to the various memory means and said resettable clock; whereby unauthorized alteration of the statistics stored in said clearable memory means is detected. - View Dependent Claims (2, 3)
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Specification