Digital data memory unit and memory unit array

• US 5,257,220 A
• Filed: 03/13/1992
• Issued: 10/26/1993
• Est. Priority Date: 03/13/1992
• Status: Expired due to Fees

• Current Assignee: The Research Foundation for The State University of New York (State University of New York)
• Original Assignee: The Research Foundation for The State University of New York (State University of New York)
• Inventors: Palumbo, Paul W., Shin, Yong-Chul, Demjanenko, Victor, Sridhar, Ramalingam, Srihari, Sargur N.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/850,644
• Time in Patent Office: 592 Days
• Field of Search: 365/49, 365/168, 365/189.07, 365/195, 365/233, 365/203
• US Class Current: 365/49.17
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A digital data memory unit and memory unit array, each unit of which can be searched in accordance with the contents thereof and updated, utilizes a digital storage element in the form of a register, latch, or memory cell, a comparator and control logic. Data is presented to the units in parallel on data lines and compare data is supplied in parallel to the units along other data lines. Parallel search of data in each unit, with multiple updates in units where the stored data matches the compare data, occurs rapidly and in one clock cycle (e.g., approximately 50 nanoseconds). The control logic responds to a match output from the comparator and an update enable pulse to enable a new data word on the data lines to be written into the digital storage element of the unit. The memory unit array is useful in image processing for storing pixel values and searching and updating these values in the process of image analysis to recognize certain images.

Claims

1. A content controlled updatable data memory unit, which is updatable during an update pulse cycle, and which comprises means for storing a first input dataword;

and means for enabling said storing means to be updated to store a second input dataword which comprises means connected to said storing means for comparing said first word with a third word, and control means responsive to an update enable pulse which changes state during said cycle for enabling said storing means to be updated to store said second word when said first and third word match.

2. The memory unit according to claim 1 further comprising a plurality of units identical to said unit and dispose therewith in an array, and means for operating said enabling means of all of said units simultaneously, whereby updates in a multiplicity of said units can occur at the same time.

3. The memory unit array according to claim 2 further comprising means for addressing said units in said array for selectably enabling writing of first data words into said storing means of different ones of said units and for selectably reading the datawords stored in different ones of said units.

4. The memory unit according to claim 1 or the memory unit array according to claim 2 further comprising means included in said control means for inhibiting storing of data words in said unit or units except when said comparing means provides an output representing said match.

5. The unit according to claim 1 wherein said storage means of said unit is a digital storage element having an input for enabling the writing of said datawords therein which input is connected to said update enable pulse responsive means.

6. The memory unit array according to claim 2 wherein said storage means of the units of said array are digital storage elements and all of the units of said array have an input for enabling each digital storage element for writing of said datawords therein and connected to said update enable responsive means of the respective units.

7. The memory unit according to claim 1 or the memory unit array according to claim 2 wherein said comparing means is a comparator providing an output bit representing the presence or absence of a match, said control means comprises a digital storage element for storing said output bit, means for applying said enable pulse to enable said digital storage element to be set to the value of said output bit at the beginning of said update pulse cycle, and a gate responsive to the bits stored in said digital storage element and said update enable pulse for applying said update enable pulse to said storing means for enabling updating thereof, when said bit corresponds to the presence of said match and the occurrence of said enable pulse in said cycle after the beginning thereof.

8. The memory unit array according to claim 2 further comprising means for providing a match output signal when a match is detected in any of said units.

11. The unit according to claim 1 or 2 wherein said comparing means has an output, and means for precharging said output and discharging said output when said storing means is enabled.

9. A memory unit containing a comparator and a digital storage element, which unit is accessed during each of a plurality of successive clock pulse periods by four signal lines, namely a data line, a comparand line, a write line and a match line, said unit comprising an update line and update control means responsive to signals from the write, update and match lines for providing an output which enables the contents of the digital storage element to be updated from said data line during any one of said clock periods upon occurrence therein of said signals from both said match line and said update line.

10. The memory unit according to claim 9 wherein said digital storage element includes a plurality of one bit memory elements, and said digital storage element stores a data word having a plurality of bits, each in a different memory element.