Antifuse programming by transistor snap-back

• US 5,257,222 A
• Filed: 01/14/1992
• Issued: 10/26/1993
• Est. Priority Date: 01/14/1992
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Roger R.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/821,501
• Time in Patent Office: 651 Days
• Field of Search: 257/530, 257/50, 365/96, 365/103, 365/104, 365/225.7
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

The present invention comprises a method to program antifuse elements in integrated circuits, such as programmable read-only memory (PROM) or option selections/redundancy repair on dynamic random access memories (DRAMs) by utilizing the phenomenon of transistor snap-back. Multiple programming pulses are applied to an NMOS transistor which provides access to the desired antifuse element. The first pulses applied ruptures the antifuse element causing it so become a resistive short. The second programming pulses cause the access NMOS transistor to go into snap-back thus allowing a surge of current to flow through the resistively shorted antifuse thereby lowering the resistance of the shorted antifuse element substantially allowing for less power consumption and higher reliability of the permanently programmed element.

Claims

1. A method to program a one time programmable element in an integrated circuit, said method comprising the steps of:

a) applying a first biasing voltage to a first terminal of said transistor;

b) applying a first voltage pulse to a second terminal of said transistor, said applications of first biasing voltage and said first voltage pulse cause said programmable element to rupture;

c) applying a second biasing voltage to said transistor'"'"'s first terminal, said second biasing voltage is at a potential less than that of said first biasing voltage; and

d) applying a second voltage pulse to said transistor'"'"'s second terminal thereby causing transistor snap-back which allows a surge of current to flow through said ruptured element.

2. The method of claim 1 wherein said programmable element is a programmable antifuse.

3. The method of claim 1 wherein said programmable element is a programmable fuse.

4. The method of claim 1 wherein said integrated circuit is a non-volatile memory device.

5. The method of claim 4 wherein said non-volatile memory device is a programmable read only memory.

6. The method of claim 1 wherein said integrated circuit is a dynamic random access memory.

7. The method of claim 1 wherein said transistor is a field effect metal oxide transistor.

8. The method of claim 7 wherein said field effect metal oxide transistor is an n-channel device with said first terminal being a gate terminal and said second terminal being a drain terminal.

9. The method of claim 7 wherein said field effect metal oxide transistor is an n-channel device with said first terminal being a drain terminal and said second terminal being a gate terminal.

10. The method of claim 1 wherein the difference between said first biasing voltage and said first voltage pulse is greater than the threshold voltage of said transistor, thereby turning on said transistor.

11. The method of claim 1 wherein the difference between said second biasing voltage and said second voltage pulse is greater than the threshold voltage of said transistor, thereby forcing said transistor to operate in said snap-back condition.

12. A method to program a one time programmable antifuse element in an integrated circuit, said method comprising the steps of:

a) applying a first biasing voltage to a first transistor'"'"'s terminal;

b) applying a first voltage pulse to a second terminal of said transistor, said applications of first biasing voltage and said first voltage pulse cause said antifuse element to rupture thereby becoming a resistive short;

c) applying a second biasing voltage to said transistor'"'"'s first terminal, said second biasing voltage being at a potential less than that of said first biasing voltage; and

d) applying a second voltage pulse to said second transistor terminal thereby causing transistor snap-back which allows a surge of current to flow through said resistive short and thereby reducing the resistance by approximately one order of magnitude.

13. The method of claim 12 wherein said integrated circuit is a non-volatile memory device.

14. The method of claim 13 wherein said non-volatile memory device is a programmable read only memory.

15. The method of claim 12 wherein said integrated circuit is a dynamic random access memory.

16. The method of claim 12 wherein said transistor is a field effect metal oxide transistor.

17. The method of claim 16 wherein said field effect metal oxide transistor is an n-channel device with said first terminal being a gate terminal and said second terminal being a drain terminal.

18. The method of claim 16 wherein said field effect metal oxide transistor is an n-channel device with said first terminal being a drain terminal and said second terminal being a gate terminal.

19. The method of claim 12 wherein said first and second biasing voltages are applied via a digit line and said first and second voltage pulses are applied via a word line.

20. The method of claim 12 wherein said first biasing voltage is approximately 16 v and said first voltage pulse is approximately 14 v.

21. The method of claim 12 wherein said second biasing voltage is approximately 8 v and said second voltage pulse is approximately 14 v.

22. A method to program an antifuse element in a programmable read only memory, said method comprising the steps of:

a) applying a first gate voltage via a word line to the gate of an NMOS transistor;

b) applying a first voltage pulse via a digit line to the drain of said NMOS transistor, said applications of first gate voltage and said first voltage pulse cause said antifuse element to rupture thereby becoming a resistive short;

c) applying a second gate voltage via said word line to said gate of said NMOS transistor, said second gate voltage being at a potential less than that of said first gate voltage; and

d) applying a second voltage pulse to said transistor'"'"'s drain thereby causing transistor snap-back which allows a surge of drain current to flow through said resistive short and thereby reducing the resistance by approximately one order of magnitude.