Method for manufacturing a semiconductor device using a circuit transfer film

• US 5,258,325 A
• Filed: 02/13/1992
• Issued: 11/02/1993
• Est. Priority Date: 12/31/1990
• Status: Expired due to Term

• Current Assignee: Kopin Corporation
• Original Assignee: Kopin Corporation
• Inventors: Spitzer, Mark B., Vu, Duy-Phach, Jacobsen, Jeffrey, Zavracky, Paul M., Dingle, Brenda, Salerno, Jack P.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/834,849
• Time in Patent Office: 628 Days
• Field of Search: 437/205, 437/208, 437/86, 437/966, 437/974, 156/DIG. 88
• US Class Current: 438/107
• CPC Class Codes: A61B 3/113 for determining or recording eye movement
• CPC Class Codes: G02B 2027/0132 comprising binocular systems
• CPC Class Codes: G02B 2027/0138 comprising image capture systems, e.g. camera
• CPC Class Codes: G02B 2027/0187 slaved to motion of at least a part of the body of the user, e.g. head, eye
• CPC Class Codes: G02B 2027/0198 System for aligning or maintaining alignment of an image in a predetermined direction
• CPC Class Codes: G02B 27/0093 with means for monitoring data relating to the user, e.g. head-tracking, eye-tracking
• CPC Class Codes: G02B 27/0172 characterised by optical features
• CPC Class Codes: G02B 5/30 Polarising elements light-modulating devices with active elements G02F1/00
• CPC Class Codes: G02F 1/13336 Combining plural substrates to produce large-area displays, e.g. tiled displays
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13613 the semiconductor element being formed on a first substrate and thereafter transferred to the final cell substrate
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G09G 2300/023 Display panel composed of stacked panels
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2340/0464 Positioning
• CPC Class Codes: G09G 2370/042 for monitor identification
• CPC Class Codes: G09G 3/30 : using electroluminescent panels
• CPC Class Codes: G09G 3/32 : semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/36 : using liquid crystals
• CPC Class Codes: G09G 3/3607 : for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 : Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 : using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 21/8221 : Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2221/68359 : used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 : used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 : used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0756 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/10 : the devices having separate containers
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 : the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01065 : Terbium [Tb]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01S 5/0217 : Removal of the substrate
• CPC Class Codes: H01S 5/423 : having a vertical cavity
• CPC Class Codes: H04N 5/70 : Circuit details for electroluminescent devices
• CPC Class Codes: H04N 5/7441 : the modulator being an array of liquid crystal cells
• CPC Class Codes: H04N 5/7491 : of head mounted projectors
• CPC Class Codes: H04N 9/3141 : Constructional details thereof details not peculiar to the presence of an electronic spatial light modulator G03B21/14
• CPC Class Codes: H05B 33/12 : Light sources with substantially two-dimensional radiating surfaces

Abstract

The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of high density and complexity. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in modules.

Claims

1. The process of forming multi-function electronic circuitry on a common body comprising the steps of:

a) forming a plurality of first electronic circuits, for performing a first function, in a first semiconductor film formed on a first substrate;

b) forming a plurality of second electronic circuits, for performing a second function, in a second semiconductor film formed on a second substrate;

c) separating areas of said films of said first and second substrates to form circuit tiles;

d) transferring said tiles to a common module body;

e) registering the tiles on said common module body;

f) adhering said tiles to the common module body;

g) removing the substrates from the tiles;

h) interconnecting first and second electronic circuits of said transferred tiles.

2. The process of claim 1 wherein the films are formed of silicon material from the group comprising amorphous Si, polysilicon or essentially single crystal silicon.

3. The process of claim 1 wherein the first circuits are thin film transistors and the second circuits are driver circuits.

4. The process of claim 1 wherein the circuits are formed in recrystallized polysilicon formed over a buried insulator and wherein the recrystallized silicon forms an essentially single crystal layer.

5. The process of claim 3 wherein the second circuits are formed in essentially single crystal silicon material and the first circuits are formed in Si from the group comprising amorphous or polysilicon material.

6. The process of claim 1 wherein the tiles are transferred sequentially and the substrates are removed sequentially.

7. The process of claim 1 wherein the first electronic circuits comprise thin film transistor circuits and the second electronic circuits comprise driver circuits and the common body is formed of a light transparent medium.

8. The process of claim 6 wherein the films are adhered using an ultra-violet light curing adhesive.

9. The process of claim 6 wherein an intermediate sacrificial layer is formed between the semiconductor film and the substrates to facilitate removal of the substrate.

10. The process of claim 7 wherein the tiles are formed using a process from the group comprising:

sawing, cleaving or etching the substrates.

11. The process of forming multi-function electronic circuitry on a common body comprising the steps of:

a) forming a plurality of first electronic circuits, for performing a first function, in a first semiconductor film formed on a first substrate;

b) forming a plurality of second electronic circuits, for performing a second function, in a second semiconductor film formed on a second substrate;

c) separating areas of said films of said first and second substrates to form circuit tiles and transferring said tiles to a body;

d) removing the substrates from the tiles;

e) transferring said circuit tiles and said body to said common body; and

f) removing said body.

12. The process of claim 11 wherein the films are formed of silicon material from the group comprising amorphous Si, polysilicon or single crystal silicon.

13. The process of claim 11 wherein the first circuits are transistors and the second circuits are driver circuits.

14. The process of claim 11 wherein the circuits are formed in recrystallized polysilicon formed over a buried insulator and wherein the recrystallized polysilicon forms an essentially single crystal layer.

15. The process of claim 13 wherein the second circuits are formed in essentially single crystal silicon material and the first circuits are formed in Si from the group comprising amorphous or polysilicon material.

16. The process of claim 11 wherein the tiles are transferred sequentially and the substrates are removed sequentially.

17. The process of claim 11 wherein the first electronic circuits comprise thin film transistor circuits and the second electronic circuits comprise driver circuits and the common body is formed of a light transparent medium.

18. The process of claim 16 wherein the films are adhered using an ultra-violet light curing adhesive.

19. The process of claim 16 wherein an intermediate sacrificial layer is formed between the semiconductor film and the substrates to facilitate removal of the substrate.

20. The process of claim 17 wherein the tiles are formed using a process from the group comprising:

sawing, cleaving or etching.

21. Apparatus for performing multiple electronic functions comprising:

a) a common module body;

b) first tiles bonded to said body having first circuits formed therein of silicon, said first circuits having elements for performing a first electronic function;

c) second tiles bonded to said body having second circuits formed therein on thin-film silicon, said second circuits having elements for performing a second electronic function; and

d) interconnection means for connecting the elements of first and second circuits.

22. The apparatus of claim 21 wherein the silicon is comprised of material from the group comprising:

amorphous, poly or single crystal.

23. The apparatus of claim 21 wherein the first circuits comprise thin-film transistors and the second circuits comprise driver circuits and wherein the interconnections connect the transistors to an array driven by the driver circuits.

24. The apparatus of claim 23 wherein the common module body comprises a portion of an active matrix liquid crystal display.

25. The process of forming electronic circuitry on a common body comprising the steps of:

a) forming a plurality of first electronic circuits, for performing a first function, in a first semiconductor film formed on a first substrate;

b) separating areas of said film of said first substrate to form circuit tiles;

c) transferring said tiles to a common body; and

d) removing the substrates from the tiles.

26. The process of claim 25 wherein the films are formed of material from the group comprising amorphous Si, polysilicon or essentially single crystal silicon.

27. The process of claim 26 wherein the first circuits are thin film transistors.

28. The process of forming electronic circuitry on a common body comprising the steps of:

a) forming a plurality of first electronic circuits, for performing a first function, in a first semiconductor film formed on a first substrate;

b) separating areas of said film of said first substrate to form circuit tiles and transferring said tiles to a transfer body;

c) removing the substrates from the tiles; and

d) transferring said circuit tiles to said common body.