Ring signal detection circuit

• US 5,258,721 A
• Filed: 08/27/1990
• Issued: 11/02/1993
• Est. Priority Date: 08/27/1990
• Status: Expired due to Fees

• Current Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Zanders, Gary V.
• Primary Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/573,413
• Time in Patent Office: 1,163 Days
• Field of Search: 328/133, 328/134, 328/138, 307/525, 307/526, 307/522, 377/28, 377/47, 377/107
• US Class Current: 327/18
• CPC Class Codes: H04M 11/066 Telephone sets adapted for data transmision

Abstract

A telephone network interface integrated circuit with digitally based loop current detection and digitally based ring signal detection. The ring signal detection includes discrimination with a cutoff frequency of about 13 Hz to distinguish ring signals from dialing signals. The discrimination includes filtration followed by triggering an oscillator for one time period and checking whether the number of oscillations exceeds a threshold.

Claims

1. An integrated circuit, comprising:

(a) an input terminal for receiving a digital signal having a signal frequency;

(b) an output terminal for indication of whether said signal frequency is greater than a cutoff frequency;

(c) a storage cell coupled to said output terminal;

(d) a counter counting at a sampling frequency;

(e) first circuitry connected to said counter, said first circuitry outputting a reset signal to said storage cell when said counter contains the value N (a positive integer) but not when said counter contains any value in the range 0 to N-1, N is approximately equal to the quotient of said sampling frequency divided by said cutoff frequency;

(f) second circuitry coupled to said input terminal, said second circuitry outputting a reset signal to said counter and a storage signal to said storage cell once each period of said digital signal;

(g) said second circuitry includes a one-shot that is fired by the falling edge of said digital signal'"'"'s pulses;

(h) said falling edge of said digital signal'"'"'s pulse is filtered by a series of flip-flops clocked at said sampling frequency prior to firing said one-shot;

(i) whereby, said storage cell outputs a signal to said output terminal if and only if said signal frequency is greater than said cutoff frequency.

2. The integrated circuit of claim 1, wherein:

(a) said storage cell is a series of flip-flops with a fixed input to the first in said series, said flip-flops clocked by said one-shot.

3. The integrated circuit of claim 1, wherein:

(a) N is in the order of 76; and

(b) said sampling frquency is about 1 KHz.

4. A frequency detector, comprising:

(a) a digital signal input terminal;

(b) a counter counting at a sampling frequency, said counter outputting a signal when the count reaches N, with N a predetermined positive integer;

(c) a digital filter coupled between said input terminal and a reset input for said counter, a signal at said reset input changing the count of said counter to 0; and

(d) an output terminal coupled to said counter and receiving said signal when the count reaches N;

(e) whereby said output terminal will have a signal indicating a count of at least N if and only if a digital signal at said input terminal has a frequency less than said sampling frequency divided by N.

5. The detector of claim 4, wherein:

(a) said filter comprises flip-flops in series and clocked at said sampling frequency.

6. The detector of claim 5, wherein:

(a) said sampling frequency is about 1 KHz; and

(b) N is about 76.