Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories

• US 5,258,986 A
• Filed: 09/19/1990
• Issued: 11/02/1993
• Est. Priority Date: 09/19/1990
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Zerbe, Jared L.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): CHUNG, PHUNG M
• Application Number:
  US07/585,334
• Time in Patent Office: 1,140 Days
• Field of Search: 371/21.2, 371/21.1.25.1, 371/24, 371/22.5, 371/15.1, 371/21.3, 371/27, 365/201
• US Class Current: 714/719
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

RAM Built-In Self-Test logic is presented that utilizes a linear feedback shift register (LFSR) to generate data. Preferably, an LFSR is also utilized for address generation during memory self-testing. More than one cycle is implemented with offset of successive data sequences relative to address sequences to increase fault coverage. Memory storage is utilized in the data generation to enable a reduced area of the data generation circuitry.

Claims

1. A method of testing memory having a set of M memory locations, said method comprising the steps of:

(a) generating a first sequence F_k that is pseudorandom;

(b) generating a second sequence S_k ;

one of said first and second sequences is utilized as an address sequence A_k and the other of said first and second sequences is utilized as a data sequence D_k ;

(c) for k=1 to some integer N, storing a kth data word D_k in a memory location at address A_k ;

(d) for a sequence of values of k=1 to some integer L, comparing a value of data actually stored in the memory location at address A_k with a value of the data word D_k that was to be stored there to determine if there has been an error in storing this data word in this memory location;

(e) generating a third sequence T_k that is pseudorandom; and

repeating steps (c) and (d) with third sequence T_k in place of first sequence F_k.

2. A method as in claim 1 wherein N equals M and each of the N data words D_k is stored in a uniquely associated address A_k, so that every memory location has data stored therein by step (c).

3. A method as in claim 1 wherein T_k =F_r where r=(k+q) Mod M for some integer q, whereby the third sequence T_k is just an offset version of the first sequence F_k :

4. A method as in claim 1 wherein step (b) comprises the step of generating the second sequence S_k with an m-bit counter.

5. A method as in claim 1 wherein step (a) comprises generating the first sequence F_k with a linear feedback shift register.

6. A method as in claim 5 wherein step (e) comprises generating the third sequence T_k with a linear feedback shift register.

7. A method as in claim 6 wherein the same linear feedback shift register is utilized to generate the first and third sequences.

8. A method as in claim 7 wherein the first and third sequences are utilized as addresses.

9. A method as in claim 8 wherein said linear feedback shift register also generates addresses utilized in step (d).

10. A method as in claim 9 wherein L is equal to M-q, for some integer q, and wherein said linear feedback shift register repeatedly generates the same sequence of addresses so that T_k =F_r, where r=k-q mod M.

11. A method as in claim 10 wherein N=M, wherein q=1 and wherein said linear feedback shift register generates a set of M=2^m addresses, for some integer m, in step (a) and (e) and generates 2^m -1 addresses in step (d).

12. A method as in claim 5 wherein step (b) comprises the step of generating the third sequence T_k with a linear feedback shift register.

13. A method as in claim 12 wherein the same linear feedback shift register is utilized to generate the first and second sequences.

14. A method as in claim 13 wherein a first subset of a set of Q output lines from said linear feedback shift register provide said address A_k and a subset of P output lines from said linear feedback shift register provide said data D_k.

15. A method as in claim 1 wherein the sequence that is utilized as the data sequence is generated by a linear feedback shift register that utilizes a memory data register of said memory as storage elements of the linear feedback shift register.

16. A method as in claim 1 wherein step (d) utilizes a core of said memory as a source of a next state data element.

17. A memory having built-in self-test logic, said memory comprising:

a memory core having M memory locations;

means for generating a first sequence F_k that is pseudorandom, a second sequence S_k and a third sequence T_k that is pseudorandom;

one of the first and second sequences functions as an address sequence A_k and the other functions as a data sequence D_k ;

means, for each value of k=1, . . . , M, for storing the kth data element D_k in a location in said memory core at address A_k determined from the first and second sequences and also for storing the kth data element D_k in a location in said memory core at address A_k determined from said second and third sequences; and

means for comparing expected values in said memory core with actual values stored in this memory core.

18. A memory as in claim 17 wherein T_k equals F_r where r=k-q mod M for some integer q.

19. A memory as in claim 17 wherein said means for generating the first, second and third sequences includes a counter for generating the second sequence.

20. A memory as in claim 17 wherein said means for generating the first, second and third sequences includes a linear feedback shift register for generating pseudorandom sequences.

21. A memory as in claim 20 wherein said linear feedback shift register generates both the first and third sequences.

22. A memory as in claim 21 wherein said first and third sequences are utilized as addresses.

23. A memory as in claim 22 wherein said linear feedback shift register also generates addresses utilized by said means for comparing.

24. A memory as in claim 23 wherein said linear feedback shift register further comprises means for altering a length of pseudorandom sequence produced by this linear feedback shift register.

25. A memory as in claim 24 wherein said linear feedback shift register can produce sequences of length 2^m and length 2^m -1 for some integer m.

26. A memory as in claim 25 wherein M=2^m.

27. A memory as in claim 20 wherein said addresses are produced on a set of Q output lines of said linear feedback shift register and said data is produced on a set of P output lines of said linear feedback shift register.

28. A memory as in claim 20 wherein said linear feedback shift register utilizes a memory data register of said core memory as storage elements of this linear feedback shift register.

29. A memory as in claim 20 wherein said core memory is a dual port core memory and wherein said linear feedback shift register is formed from memory elements within said core and additional logic.