Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like

• US 5,259,006 A
• Filed: 08/20/1991
• Issued: 11/02/1993
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Systems, Inc.
• Inventors: Price, Roderick A., Thielges, Bart C.
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): TSE, YOUNG TOI
• Application Number:
  US07/747,740
• Time in Patent Office: 805 Days
• Field of Search: 375/106, 375/107, 375/118, 375/111, 377/78, 377/80, 307/269, 371/1
• US Class Current: 375/356
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user'"'"'s original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.

Claims

1. A method for preventing hold time violations in a sequential logic circuit being implemented from logic configuration data, said sequential logic circuit including a plurality of user clocked flip-flop devices, each of said user clocked flip-flop devices having a source data path associated therewith and being controlled from a corresponding clock signal, each of said user clocked flip-flop devices including a data input connected to a data signal input node for receiving data signals, a clock input for receiving said corresponding clock signal, and an output, said logic circuit characterized by an undetermined amount of clock skew between said plurality of user clocked flip-flop devices, said method comprising the steps of:

providing in said source data path associated with each of said user clocked flip-flop devices, a corresponding synchronizer flip-flop device having a data input connected to the data signal input node associated with its corresponding user clocked flip-flop device, an output connected to the data input of its corresponding user clocked flip-flop device, and a clock input;

driving each said synchronizer flip-flop device with a synchronizing clock signal derived from said corresponding clock signal associated with its corresponding user clocked flip-flop device; and

,

delaying each of said corresponding clock signals to form a plurality of delayed corresponding clock signals and applying said delayed corresponding clock signals to the clock inputs of each of said user clocked flip-flop devices.

2. The method of claim 1 wherein the step of delaying each of said corresponding clock signals includes the steps of first determining the amount of clock skew in the sequential logic circuit described by said logic configuration data and adding enough delay to each of said corresponding clock signals such that all of said synchronizing clock signals arrive at the clock inputs of each said synchronizer flip-flop device before any of said delayed corresponding clock signals arrive at the clock input of any user clocked flip-flop device.

3. A method for preventing hold time violations in a digital logic circuit being implemented from logic circuit configuration data, said digital logic circuit including a plurality of user clocked transparent latches having a source data path associated therewith and being controlled from a corresponding clock signal having a latching edge, each of said user clocked transparent latches having a data input for receiving data signals from a data signal input node, a clock input for receiving said corresponding clock signal and an output, said logic circuit characterized by an undetermined amount of clock skew between said plurality of user clocked transparent latches, said method comprising the steps of:

providing in said source data path associated with each of said user clocked transparent latches, a corresponding synchronizer clocked transparent latch having a data input connected to the data input signal node associated with its corresponding user clocked transparent latch, an output connected to the data input of its corresponding user clocked transparent latch, and a clock input;

driving each said synchronizer clocked transparent latch with a synchronizing clock signal derived from said corresponding clock signal associated with each user clocked transparent latch; and

,

delaying the latching edge of each of said corresponding clock signals to form a plurality of delayed latching edge corresponding clock signals and applying corresponding ones of said delayed latching edge corresponding clock signals to the clock inputs of each of said user clocked transparent latches.

4. The method of claim 3 wherein the step of delaying the latching edge of said corresponding clock signals includes the steps of first determining the amount of clock skew in the sequential logic circuit described by said logic configuration data and adding enough delay to the latching edge of each of said corresponding clock signals such that all of the latching edges of said synchronizing clock signals arrive at the clock inputs of each said synchronizer clocked transparent latch before any latching edge of any of said delayed latching edge corresponding clock signals arrive at the clock input of any user clocked transparent latch.

5. The method of claim 3 wherein the width of said synchronizing clock signal is adjusted by first determining the amount of clock skew in the sequential logic circuit described by said logic configuration data, then setting the width of said synchronizing clock signal such that its unlatching edge always occurs at the clock input of said synchronizer clocked transparent latch after the latching edge of said delayed latching edge corresponding clock signal arrives at the clock input of the corresponding user clocked transparent latch for all user clocked transparent latches in the sequential logic circuit described by said logic configuration data.

6. A method for preventing hold time violations in a sequential logic circuit being implemented from logic configuration data, said sequential logic circuit including a plurality of user clocked flip-flop devices, each of said user clocked flip-flop devices having a source data path associated therewith and being controlled from a corresponding clock signal, each of said user clocked flip-flop devices having a data input for receiving data signals from a data input signal node, a clock input for receiving said corresponding clock signal, and an output, said logic circuit characterized by an undetermined amount of clock skew between said plurality of user clocked flip-flop devices, said method comprising the steps of:

providing in said source data path associated with each of said user clocked flip-flop devices, a corresponding synchronizer clocked transparent latch device having a data input connected to the data input signal node associated with its corresponding user clocked flip-flop device, an output connected to the data input of its corresponding user clocked flip-flop device, and a clock input;

driving the clock input of each said synchronizer clocked transparent latch device with a synchronizing clock signal derived from said corresponding clock signal associated with its corresponding user clocked flip-flop device; and

,

delaying each of said corresponding clock signals to form a plurality of delayed corresponding clock signals and applying said delayed corresponding clock signals to the clock inputs of each of said user clocked flip-flop devices.

7. The method of claim 6 wherein the step of delaying said corresponding clock signals includes the steps of first determining the amount of clock skew in the sequential logic circuit described by said logic configuration data and adding enough delay to each of said corresponding clock signals such that all of the latching edges of said synchronizing clock signals arrive at the clock inputs of each said synchronizer clocked transparent latch before any delayed corresponding clock signals arrive at the clock input of any user clocked flip-flop device.

8. The method of claim 6 wherein the width of said synchronizing clock signal is adjusted by first determining the amount of clock skew in the sequential logic circuit described by said logic configuration data, then setting the width of said synchronizing clock signal such that its unlatching edge always occurs at the clock input of said synchronizer clocked transparent latch after the delayed corresponding clock signal arrives at the clock input of the corresponding user clocked flip-flop device for all user clocked flip-flop devices in the sequential logic circuit described by said logic configuration data.