Phase locked loop frequency synthesizer

• US 5,259,007 A
• Filed: 06/16/1992
• Issued: 11/02/1993
• Est. Priority Date: 06/19/1991
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yamamoto, Tetsuo
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/899,416
• Time in Patent Office: 504 Days
• Field of Search: 375/81, 375/97, 375/119, 375/120, 331/1 A, 331/18, 331/25, 331/51, 307/511, 307/514, 307/516, 307/526, 328/16, 328/55
• US Class Current: 375/376
• CPC Class Codes: H03L 2207/10 Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/185 using a mixer in the loop H03L7/187 - H03L7/195 take precedence

Abstract

A PLL Frequency Synthesizer includes a reference signal source which outputs a reference frequency signal. A phase of the signal out of the reference signal source and a phase of a signal coming back through a feed-back loop are compared by a phase comparator which detects the phase difference between them. The output of the comparator is integrated by a low pass filter which generates a voltage output corresponding to the phase difference. A voltage controlled oscillator is also provided to the PLL Frequency Synthesizer of the invention, an output frequency of which is controlled by the amplitude of a signal out of the low pass filter. The output signal out of the voltage controlled oscillator is divided by a variable divider whose denominator can be variable from outside. A frequency multiplier is provided between the phase comparator and the variable divider so as to multiply the frequency of signal derived from the variable divider.

Claims

1. A Phase Locked Loop (PLL) Frequency Synthesizer comprising:

a reference signal source for producing a referenced frequency signal,

a phase comparator for comparing a phase of a signal from said reference signal source with a phase of a signal from a feed-back loop and producing an output indicative of a phase difference between said phases,

a low pass filter for integrating said output of said comparator to generate a filter output with a voltage corresponding to said phase difference,

a voltage controlled oscillator to generate an oscillator output with a frequency controlled by said filter output,

first variable frequency dividing means for dividing a frequency of said oscillator output by a predetermined divide ratio, and

a frequency multiplier connected between said phase comparator and said variable frequency dividing means to multiply the frequency of the signal derived from said variable frequency dividing means.

2. A PLL Frequency Synthesizer according to claim 1, wherein said frequency multiplier includes a monolithic filter to select harmonics of the output of said variable frequency divider.

3. A PLL Frequency Synthesizer according to claim 1, wherein said frequency multiplier includes a double balanced mixer to double the frequency of a signal from said variable frequency dividing means.

4. A PLL Frequency Synthesizer according to claim 1, wherein said reference signal source includes a crystal oscillator and a second variable frequency dividing means.