Method to form self-aligned gate structures and focus rings

• US 5,259,799 A
• Filed: 11/17/1992
• Issued: 11/09/1993
• Est. Priority Date: 03/02/1992
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lowrey, Tyler A., Doan, Trung T., Rolfson, J. Brett, Cathey, David A.
• Primary Examiner(s): Seidel, Richard K.
• Assistant Examiner(s): Knapp, Jeffrey T.
• Application Number:
  US07/977,477
• Time in Patent Office: 357 Days
• Field of Search: 445/24, 445/49, 445/50
• US Class Current: 445/24
• CPC Class Codes: H01J 2209/0226 Sharpening or resharpening of emitting point or edge
• CPC Class Codes: H01J 2329/00 Electron emission display panels, e.g. field emission display panels
• CPC Class Codes: H01J 9/025 of field emission cathodes

Abstract

A selective etching and chemical mechanical planarization process for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a first conformal layer, iii) deposited with a conductive material layer, iv) deposited with a second conformal insulating layer, v) deposited with a focus electrode ring material layer, vi) optionally deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose a portion of the second conformal layer, viii) etched to form a self-aligned gate and focus ring, and thereby expose the emitter tip, afterwhich xi) the emitter tip may be coated with a low work function material.

Claims

1. A process for the formation of self-aligned gate and focus ring structures around an electron emitter, said process comprising the following steps:

planarizing at least one electron emitter overlaid with insulating and conductive layers, said planarizing involving chemical mechanical means; and

selectively removing said insulating and conductive layers, thereby exposing at least a portion of said electron emitter.

2. The process according to claim 1, wherein said chemical mechanical means comprises rotation of said overlaid electron emitter against a wetted polishing surface under controlled chemical slurry, pressure, and temperature conditions.

3. The process according to claim 2, wherein said chemical slurry comprises a polishing agent.

4. The process according to claim 3, wherein said chemical slurry further comprises chemical etchants.

5. The process according to claim 4, wherein said insulating and conductive layers are selectively removed by etching.

6. The process according to claim 5, wherein said electron emitter comprises a cathode.

7. The process according to claim 6, wherein said cathode has a tip.

8. The process according to claim 7, further comprising the step of:

sharpening said tip of said cathode by oxidation.

9. The process according to claim 8, further comprising the step of:

coating said tip of said cathode with a low work function material.

10. A process for the formation of multiple grid structures around an electron emitter, said process comprising the following steps:

forming at least one cathode on a substrate;

forming at least two insulating layers superjacent said cathode;

depositing at least two conductive material layers superjacent said insulating layers;

planarizing said layers by chemical mechanical planarization (CMP); and

removing said layers to expose at least a portion of said cathode.

11. The process according to claim 10, wherein said cathode is an electron emitter, said electron emitter having a tip.

12. The process according to claim 11, further comprising the step of:

depositing a buffer material prior to subjecting the cathode to chemical mechanical planarization.

13. The process according to claim 12, wherein at least one of said insulating layers is growth through oxidation.

14. The process according to claim 13, wherein said removing further comprises the step of:

etching said at least two insulating layers thereby defining gate and focus ring structures.

15. The process according to claim 14, wherein said insulating layers are selectively etchable with respect to said conductive layers.

16. The process according to claim 15, wherein said substrate comprises at least one of polysilicon, doped polysilicon, and silicized silicon.

17. The process according to claim 16, wherein said insulating layers comprise at least one of silicon dioxide, silicon nitride, and silicon oxynitride.

18. A process for the formation of self-aligned gate and focus ring structures around an electron emitting tip, said process comprising the following steps:

forming at least one cathode on a substrate, said cathode having an emitter tip;

forming a first insulating layer superjacent said emitter tip;

depositing a conductive material layer superjacent said first insulating layer;

depositing a second insulating layer superjacent said conductive material layer;

depositing a focus electrode material layer superjacent said second insulating layer;

polishing said substrate by chemical mechanical planarization (CMP) to expose at least a portion of said conductive material layer; and

selectively removing said layers to expose the emitter tip.

19. The process according to claim 18, wherein said first and second insulating layers are selectively removed by etching, said insulating layers being selectively etchable with respect to said conductive material layer and said focus electrode layer.

20. The process according to claim 19, wherein the chemical mechanical planarization (CMP) step is performed with an abrasive compound in a polishing slurry.