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Integrated circuit fabrication process to reduce critical dimension loss during etching

  • US 5,259,924 A
  • Filed: 04/08/1992
  • Issued: 11/09/1993
  • Est. Priority Date: 04/08/1992
  • Status: Expired due to Term
First Claim
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1. An integrated circuit fabrication process comprising the steps of:

  • providing a layer of a first material;

    forming a layer of a second material having a thickness less than 300 angstroms determined only by the selectivity of said first etch process to said second material, said layer of second material covering said layer of a first material and having a fundamentally different etch chemistry from said first material;

    forming a layer of a third material covering said layer of a second material having an etch chemistry similar to the etch chemistry of said first material;

    patterning said third material using a first anisotropic etch process to remove portions of said third material to expose selected areas of said second material;

    removing the exposed areas of said second material using a second etch process having an etch chemistry fundamentally different from the chemistry of said first anisotropic etch process.

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