Integrated circuit fabrication process to reduce critical dimension loss during etching

• US 5,259,924 A
• Filed: 04/08/1992
• Issued: 11/09/1993
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Niroomand, Ardavan, Fazan, Pierre C., Blalock, Guy T., Mathews, Viju K.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): DANG, TRUNG Q
• Application Number:
  US07/865,087
• Time in Patent Office: 580 Days
• Field of Search: 156/643, 156/653, 156/651, 156/652
• US Class Current: 438/702
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks

Abstract

A pad oxide is formed on a silicon substrate followed by a layer of polysilicon about 100 Å thick. A silicon nitride layer is formed over said polysilicon layer then patterned with a first, fluorine-based, etch process to expose selected areas of the polysilicon layer. Then the exposed areas of polysilicon are removed using a second, chlorine-based, etch process fundamentally different from the first etch process. The high selectivity of the first etch process for nitride combined with the high selectivity of the second etch process for oxide, results in negligible CD loss in the overall process.

Claims

1. An integrated circuit fabrication process comprising the steps of:

providing a layer of a first material;

forming a layer of a second material having a thickness less than 300 angstroms determined only by the selectivity of said first etch process to said second material, said layer of second material covering said layer of a first material and having a fundamentally different etch chemistry from said first material;

forming a layer of a third material covering said layer of a second material having an etch chemistry similar to the etch chemistry of said first material;

patterning said third material using a first anisotropic etch process to remove portions of said third material to expose selected areas of said second material;

removing the exposed areas of said second material using a second etch process having an etch chemistry fundamentally different from the chemistry of said first anisotropic etch process.

2. The process of claim 1 wherein said first material is silicon dioxide, said second material is polysilicon, and said third material is silicon nitride.

3. The process of claim 2 wherein said first anisotropic etch process is fluorine-based etch process and said second etch process is a chlorine-based etch process.

4. An integrated circuit fabrication process comprising the steps of:

providing a silicon substrate;

forming a layer silicon oxide on said silicon substrate;

forming a layer of polysilicon less than 300 Å

thick over said silicon oxide layer;

forming a silicon nitride layer over said polysilicon layer;

patterning said silicon nitride layer with a first anisotropic etch process to expose selected areas of said polysilicon layer;

removing said exposed areas of polysilicon using a second etch process fundamentally different from said first anisotropic etch process.

5. A process as in claim 4 wherein said first anisotropic etch process is fluorine-based etch process and said second etch process is a chlorine-based etch process.

6. An integrated circuit fabrication process comprising the steps of:

providing a layer of a first material;

forming a layer of a second material having a thickness of less than 300 angstroms covering said layer of first material and having a fundamentally different etch chemistry from said first material;

forming a layer of a third material covering said layer of second material and having an etch chemistry similar to the etch chemistry of said first material;

forming a patterned photoresist layer on said layer of a third material, said patterned photoresist layer including an opening that exposes selected areas of said third materials;

patterning said third material through said opening using a first etch process to remove said selected areas of said third material and to expose selected areas of said second material, wherein said first etch process does not isotropically etch the photoresist layer or substantially etch the second material layer;

removing the exposed areas of said second material through said opening using a second etch process having an etch chemistry fundamentally different from said first etch process.

7. The process of claim 6 wherein said layer of second material has a minimum thickness determined only by the selectivity of said first etch process to said second material.

8. An integrated circuit fabrication process comprising the steps of:

providing a semiconductor wafer;

forming a first layer comprising silicon oxide on the semiconductor wafer;

forming a second layer comprising a material having a fundamentally different etch chemistry from said first layer, wherein said second layer covers said first layer and is less than about 300 Å

thick;

forming a third layer comprising silicon nitride covering said second layer, wherein said second layer has a fundamentally different etch chemistry from said third layer;

forming a photoresist layer covering said third layer;

removing a portion of the photoresist layer to expose selected areas of said third layer;

removing said selected areas of said third layer using a fluorine-based plasma-enhanced anisotropic etch process to expose selected portions of said second layer; and

removing said selected portions of said second layer using a plasma-enhanced etch process based on one of the groups consisting of chlorine or hydrogen bromide.

9. The process of claim 8 wherein said second layer comprises polysilicon.