Programmable logic element interconnections for programmable logic array integrated circuits
First Claim
1. In a programmable logic array having plurality of programmable logic elements, each of which has at least one programmable logic element output lead and at least one of which has at least one programmable logic element input lead, means for selectively connecting any one of said programmable logic element output leads to said programmable logic element input lead comprising:
- a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead;
means for connecting each of said programmable logic element output leads to a respective one of said multiplexer input leads; and
means for connecting said multiplexer output lead to said programmable logic element input lead, the programmable logic elements being arranged in an array of mutually exclusive groups, said means for connecting each of said programmable logic element output leads to a respective one of said multiplexer input leads comprising first conductors which can only be used to connect said programmable logic elements within said mutually exclusive groups, second conductors which can be used to convey signals between said mutually exclusive groups, and branch conductors connected between said multiplexer input leads and said first and second conductors, said branch conductors making fixed connections with a selected number of said first and second conductors.
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Abstract
A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
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Citations
26 Claims
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1. In a programmable logic array having plurality of programmable logic elements, each of which has at least one programmable logic element output lead and at least one of which has at least one programmable logic element input lead, means for selectively connecting any one of said programmable logic element output leads to said programmable logic element input lead comprising:
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a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead; means for connecting each of said programmable logic element output leads to a respective one of said multiplexer input leads; and means for connecting said multiplexer output lead to said programmable logic element input lead, the programmable logic elements being arranged in an array of mutually exclusive groups, said means for connecting each of said programmable logic element output leads to a respective one of said multiplexer input leads comprising first conductors which can only be used to connect said programmable logic elements within said mutually exclusive groups, second conductors which can be used to convey signals between said mutually exclusive groups, and branch conductors connected between said multiplexer input leads and said first and second conductors, said branch conductors making fixed connections with a selected number of said first and second conductors. - View Dependent Claims (2)
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3. In a programmable logic array having a plurality of programmable logic elements, each of which has at least one programmable logic element input lead and at least one programmable logic element output lead, means for selectively connecting said programmable logic element output leads to said programmable logic element input leads comprising:
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a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected to a respective one of a plurality of said programmable logic element output leads; and means for selectively connecting said multiplexer output lead to said programmable logic element input leads, wherein said programmable logic element output leads cross said programmable logic element input leads without possibility of interconnection, and wherein said means for selectively connecting comprises; a multiplexer output lead which crosses said programmable logic element input leads; and means for selectively connecting said multiplexer output lead to each of said programmable logic element input leads. - View Dependent Claims (4)
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5. Apparatus for connecting any one of a plurality of first conductors on an integrated circuit to any one of a plurality of second conductors on said circuit comprising:
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a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected to a respective one of said first conductors; and means for selectively connecting said multiplexer output leads to any of said second conductors, wherein said second conductors cross said first conductors without possibility of interconnection, wherein said multiplexer output lead crosses said second conductors, and wherein said means for selectively connecting comprises; means for selectively connecting said multiplexer output lead to each of said second conductors. - View Dependent Claims (6)
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7. Apparatus for applying a signal on any one of a plurality of first signal conductors on an integrated circuit to a signal utilization input terminal of a signal utilization device on said circuit comprising:
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a plurality of second signal conductors, each of which is selectively connectable to one conductor in a respective subplurality of said first signal conductors, each of said respective subpluralities of selectable connections to said first signal conductors being mutually exclusive; and a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected to a respective one of said second signal conductors, and said multiplexer output lead being connected to said signal utilization input terminal of said signal utilization device. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A programmable logic array device having a plurality of programmable logic elements, each of which has at least one programmable logic element input lead and at least one programmable logic element output lead, said programmable logic elements being grouped into a plurality of mutually exclusive groups, said device comprising:
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a plurality of first signal conductors uniquely associated with each of said groups for selectively connecting the programmable logic element output leads of each group to the programmable logic element input leads of that group; and a plurality of second signal conductors for selectively connecting the programmable logic element output lead of at least one of the programmable logic elements in at least one of said groups to at least one of the programmable logic element input leads of another group. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A programmable logic array integrated circuit having top, bottom, left, and aright edges, comprising:
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a plurality of horizontal conductors, each extending continuously from the left edge to the right edge of the circuit; a plurality of vertical conductors, each extending continuously from the top edge to the bottom edge of the circuit, the vertical conductors being substantially perpendicular to the horizontal conductors; and a plurality of logic array blocks disposed on the circuit in a two-dimensional array, each logic array block comprising; an equal number of substantially identical programmable logic elements, each programmable logic element having at least one programmable logic element input and at least one programmable logic element output, and a plurality of local conductors that may be selectively connected to only the programmable logic element inputs and outputs in the same logic array block, the plurality of local conductors conducting signals being between programmable logic elements within that block, wherein; the programmable logic element inputs are selectively connectable to the horizontal conductors, and the programmable logic element outputs are selectively connectable to the horizontal and the vertical conductors, the horizontal conductors only being connectable to the vertical conductors through programmable connections, each logic analog block being associated with a distinct subplurality of the horizontal conductors and a distinct subplurality of the vertical conductors, and each logic array block being disposed adjacent to the associated conductors. - View Dependent Claims (23, 24, 25, 26)
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Specification