Programmable logic element interconnections for programmable logic array integrated circuits

• US 5,260,610 A
• Filed: 09/03/1991
• Issued: 11/09/1993
• Est. Priority Date: 09/03/1991
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pedersen, Bruce B., Cliff, Richard G., Veenstra, Kerry S., Ahanin, Bahram, Heile, Francis B., Lytle, Craig S.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US07/754,017
• Time in Patent Office: 798 Days
• Field of Search: 307/465, 307/465.1, 307/243, 340/825.83, 340/825.85, 340/825.87, 364/716
• US Class Current: 326/41
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Claims

1. In a programmable logic array having plurality of programmable logic elements, each of which has at least one programmable logic element output lead and at least one of which has at least one programmable logic element input lead, means for selectively connecting any one of said programmable logic element output leads to said programmable logic element input lead comprising:

a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead;

means for connecting each of said programmable logic element output leads to a respective one of said multiplexer input leads; and

means for connecting said multiplexer output lead to said programmable logic element input lead, the programmable logic elements being arranged in an array of mutually exclusive groups, said means for connecting each of said programmable logic element output leads to a respective one of said multiplexer input leads comprising first conductors which can only be used to connect said programmable logic elements within said mutually exclusive groups, second conductors which can be used to convey signals between said mutually exclusive groups, and branch conductors connected between said multiplexer input leads and said first and second conductors, said branch conductors making fixed connections with a selected number of said first and second conductors.

2. The apparatus defined in claim 1 further comprising:

programmable means for controlling the connection made by said multiplexer.

3. In a programmable logic array having a plurality of programmable logic elements, each of which has at least one programmable logic element input lead and at least one programmable logic element output lead, means for selectively connecting said programmable logic element output leads to said programmable logic element input leads comprising:

a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected to a respective one of a plurality of said programmable logic element output leads; and

means for selectively connecting said multiplexer output lead to said programmable logic element input leads, wherein said programmable logic element output leads cross said programmable logic element input leads without possibility of interconnection, and wherein said means for selectively connecting comprises;

a multiplexer output lead which crosses said programmable logic element input leads; and

means for selectively connecting said multiplexer output lead to each of said programmable logic element input leads.

4. The apparatus defined in claim 3 wherein said means for selectively connecting said multiplexer output lead to each of said programmable logic element input leads comprises:

a programmable interconnection between said multiplexer output lead and each of said programmable logic element input leads.

5. Apparatus for connecting any one of a plurality of first conductors on an integrated circuit to any one of a plurality of second conductors on said circuit comprising:

a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected to a respective one of said first conductors; and

means for selectively connecting said multiplexer output leads to any of said second conductors, wherein said second conductors cross said first conductors without possibility of interconnection, wherein said multiplexer output lead crosses said second conductors, and wherein said means for selectively connecting comprises;

means for selectively connecting said multiplexer output lead to each of said second conductors.

6. The apparatus defined in claim 5 wherein said means for selectively connecting said multiplexer output lead to each of said second conductors comprises:

a programmable interconnection between said multiplexer output lead and each of said second conductors.

7. Apparatus for applying a signal on any one of a plurality of first signal conductors on an integrated circuit to a signal utilization input terminal of a signal utilization device on said circuit comprising:

a plurality of second signal conductors, each of which is selectively connectable to one conductor in a respective subplurality of said first signal conductors, each of said respective subpluralities of selectable connections to said first signal conductors being mutually exclusive; and

a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected to a respective one of said second signal conductors, and said multiplexer output lead being connected to said signal utilization input terminal of said signal utilization device.

8. The apparatus defined in claim 7 wherein said first signal conductors are substantially parallel to one another, wherein said second signal conductors are substantially parallel to one another and transverse to said first signal conductors, and wherein the first signal conductors in each of said subpluralities are interdigitated with the first signal conductors in each other of said subpluralities.

9. The apparatus defined in claim 7 further comprising:

programmable means for controlling the connection made by said multiplexer.

10. The apparatus defined in claim 7 wherein the selective connections between said first and second signal conductors are made by programmable interconnections between said first and second signal conductors.

11. The apparatus defined in claim 10 wherein a single programmable element controls the programmable interconnection between at least two of said second signal conductors and said first signal conductors.

12. The apparatus defined in claim 10 wherein a single programmable element controls (1) the programmable interconnection between a first of said first signal conductors and a first of said second signal conductors, and (2) the programmable interconnection between a second of said first signal conductors and a second of said second signal conductors.

13. A programmable logic array device having a plurality of programmable logic elements, each of which has at least one programmable logic element input lead and at least one programmable logic element output lead, said programmable logic elements being grouped into a plurality of mutually exclusive groups, said device comprising:

a plurality of first signal conductors uniquely associated with each of said groups for selectively connecting the programmable logic element output leads of each group to the programmable logic element input leads of that group; and

a plurality of second signal conductors for selectively connecting the programmable logic element output lead of at least one of the programmable logic elements in at least one of said groups to at least one of the programmable logic element input leads of another group.

14. The device defined in claim 13 wherein each of said second signal conductors can receive a signal from any one of an associated plurality of said programmable logic element output leads, and wherein said device further comprises:

gate means associated with each of said programmable logic element output leads for selectively applying the signal to the programmable logic element output lead that is connected to the associated second signal conductor.

15. The device defined in claim 14 further comprising:

programmable means for controlling whether or not said gate means applies the signal on the associated programmable logic element output lead to the associated second conductor.

16. The device defined in claim 13 wherein said groups are disposed on said device in a two-dimensional array, wherein said second signal conductors are substantially parallel to a first dimension of said two-dimensional array and conduct signals between groups which are arrayed substantially parallel to said first dimension, and wherein said device further comprises:

a plurality of third signal conductors substantially parallel to a second dimension of said two-dimensional array for selectively connecting the programmable logic element output lead of at least one of the programmable logic elements in a group to at least one of the programmable logic element input leads of another group, the third signal conductors conducting signals between groups which are arrayed substantially parallel to said second dimension.

17. The device defined in claim 16 further comprising:

means for selectively connecting each of said third conductors to selected ones of said second conductors in order to selectively connect to the programmable logic element input leads.

18. The device defined in claim 16 further comprising:

gate means associated with at least one of the programmable logic elements for selectively applying the signal to the programmable logic element output lead that is connected to an associated third signal conductor.

19. The device defined in claim 18 further comprising:

programmable means for controlling whether or not said gate means applies the associated programmable logic element output signal to the associated third signal conductor.

20. The device defined in claim 16 wherein at least one of said programmable logic elements comprises:

a multiplexer for selectively connecting one of a plurality of multiplexer input leads to a multiplexer output lead, a first of said multiplexer input leads being connected to the programmable logic element output lead of at least one of said programmable logic elements, a second of said multiplexer input leads being connected to one of said third signal conductors, and said multiplexer output lead being connected to one of said second signal conductors.

21. The device defined in claim 20 further comprising:

programmable means for controlling the connection made by said multiplexer.

22. A programmable logic array integrated circuit having top, bottom, left, and aright edges, comprising:

a plurality of horizontal conductors, each extending continuously from the left edge to the right edge of the circuit;

a plurality of vertical conductors, each extending continuously from the top edge to the bottom edge of the circuit, the vertical conductors being substantially perpendicular to the horizontal conductors; and

a plurality of logic array blocks disposed on the circuit in a two-dimensional array, each logic array block comprising;

an equal number of substantially identical programmable logic elements, each programmable logic element having at least one programmable logic element input and at least one programmable logic element output, and

a plurality of local conductors that may be selectively connected to only the programmable logic element inputs and outputs in the same logic array block, the plurality of local conductors conducting signals being between programmable logic elements within that block, wherein;

the programmable logic element inputs are selectively connectable to the horizontal conductors, and the programmable logic element outputs are selectively connectable to the horizontal and the vertical conductors, the horizontal conductors only being connectable to the vertical conductors through programmable connections, each logic analog block being associated with a distinct subplurality of the horizontal conductors and a distinct subplurality of the vertical conductors, and each logic array block being disposed adjacent to the associated conductors.

23. The programmable logic device defined in claim 22 wherein each programmable logic element has a flip-flop for receiving and processing data signals from the programmable logic element input.

24. The programmable logic device defined in claim 23 wherein each programmable logic element has a look-up table connected between the programmable logic element input and the flip-flop for receiving the data signals from the programmable logic element input and providing the data signals to the flip-flop.

25. The programmable logic device defined in claim 22 wherein each programmable logic element comprises:

input logic means connected to the programmable logic element input for receiving and processing data signals from a horizontal conductor that is connected to the programmable logic element input; and

switch means connected to the input logic means and connected between a horizontal conductor that is among the subplurality of the horizontal conductors that are associated with the logic array block that contains the programmable logic element and a first vertical conductor that is among the subplurality of the vertical conductors that are associated with the logic array block that contains the programmable logic element, the switch means being programmable for selectively providing a conducting path between the associated horizontal conductor and the associated first vertical conductor, between the input logic means and the associated first vertical conductor, and between the input logic means and the associated horizontal conductor, the switch means further being programmable for selectively providing the conducting path between the associated horizontal and first vertical conductors while allowing the input logic means to simultaneously provide the processed data signals to the programmable logic element output.

26. The programmable logic device defined in claim 25 wherein the switch means further is connected to a second vertical conductor that is among the subplurality of the vertical conductors that are associated with the logic array block that contains the programmable logic element, the switch means being programmable for selectively providing a conducting path between the associated horizontal and second vertical conductors while allowing the input logic means to simultaneously provide the processed data signals to the programmable logic element output.