Programmable logic array having local and long distance conductors

• US 5,260,611 A
• Filed: 05/08/1992
• Issued: 11/09/1993
• Est. Priority Date: 09/03/1991
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pedersen, Bruce B., Veenstra, Kerry, Cliff, Richard G., Ahanin, Bahram, Heile, Francis B., Lytle, Craig S.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US07/880,942
• Time in Patent Office: 550 Days
• Field of Search: 307/465, 307/465.1
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

Claims

1. A programmable logic array integrated circuit comprising:

a plurality of programmable logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being disposed on said circuit in a two dimensional array;

a first network of conductors for programmably connecting the output of substantially any of said logic modules to substantially any of said logic module inputs, said first network including a plurality of first conductors extending substantially only parallel to a first of the two dimensions of said array, a plurality of second conductors extending substantially only parallel to a second of the two dimensions of said array, and means for selectively connecting each of said first conductors to at least a respective one of said second conductors;

third and fourth conductors for respectively conveying first and second clock signals adjacent to substantially every one of said logic modules, each of said third and fourth conductors having components which extend parallel to both said first and second dimensions of said array; and

means associated with each of said logic modules for selecting the clock signal on one of said third and fourth conductors and for applying the selected clock signal to said logic module.

2. A programmable logic array integrated circuit comprising:

a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logic function of said inputs, said logic modules being grouped in a plurality of logic array blocks, said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks;

a plurality of first conductors associated with each of said blocks for selectively applying the outputs of the logic modules in the associated block to the inputs of the logic modules in that block;

a plurality of second conductors extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the adjacent row;

means for selectively applying the outputs of the logic modules in a row to the second conductors in the group adjacent to said row;

means for selectively applying the signals on the second conductors in each group to the inputs of the logic modules in the row adjacent to said group;

a plurality of third conductors extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the adjacent column;

means for selectively applying the outputs of the logic modules in each column to the third conductors in the group adjacent to said column; and

means for selectively connecting said third conductors to said second conductors;

wherein said means for selectively applying the signals on the second conductors in each group to the inputs of the logic modules in the row adjacent to said group comprises;

a plurality of fourth conductors associated with each of said blocks;

a first programmable logic connector connected between a plurality of the second conductors in the group adjacent to the row including said block and each of said fourth conductors;

programmable function control element means for controlling each first programmable logic connector to select at least one of the second conductors connected to that first programmable logic connector as a source for a signal applied to the fourth connector connected to that first programmable logic connector;

a second programmable logic connector connected between a plurality of the fourth conductors associated with each of said blocks and each input of the logic modules in said block; and

programmable function control element means for controlling each second programmable logic connector to select at least one of the fourth conductors connected to that second programmable logic connector as a source for a signal applied to the logic module input connected to that second programmable logic connector.

3. The circuit defined in claim 2 wherein each second programmable logic connector is additionally connected between a plurality of the first conductors associated with the same block with which the fourth conductors connected to that second programmable logic connector are associated and each input of the logic modules in said block, and wherein said programmable function control element means for controlling each second programmable logic connector causes that second programmable logic connector to select at least one of the first and fourth conductors connected to that second programmable logic connector as a source for a signal applied to the logic module input connected to that second programmable logic connector.

4. A programmable logic array integrated circuit comprising:

a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being grouped in a plurality of logic array blocks, said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks;

a plurality of first conductors associated with each of said blocks for selectively applying the outputs of the logic modules in the associated block to the inputs of the logic modules in that block;

a plurality of second conductors extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the adjacent row;

means for selectively applying the outputs of the logic modules in a row to the second conductors in the group adjacent to said row;

means for selectively applying the signals on the second conductors in each group to the inputs of the logic modules in the row adjacent to said group;

a plurality of third conductors extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the adjacent column;

means for selectively applying the outputs of the logic modules in each column to the third conductors in the group adjacent to said column;

means for selectively connecting said third conductors to said second conductors;

at least one universal conductor extending adjacent to all of said blocks; and

means for selectively applying a logic signal on said universal conductor to any of said logic modules.

5. The circuit defined in claim 4 wherein said means for selectively applying the logic signal on said universal conductor to any of said logic modules comprises:

at least one local conductor associated with each of said blocks;

means for selectively applying the logic signal on said universal conductor to the local conductor associated with any of said blocks; and

means for applying the signal on each local conductor to any of the logic modules in the block associated with said local conductor.

6. A programmable logic array integrated circuit comprising:

a plurality of programmable logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs;

a network of interconnection conductors for programmably conducting the output of substantially any of said logic modules to substantially any of said logic module inputs;

first and second clock signal conductors for respectively conveying first and second clock signals to substantially every one of said logic modules; and

means associated with each of said logic modules for selecting the clock signal on one of said first and second clock signal conductors for application to said logic module.

7. A programmable logic array integrated circuit comprising:

a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being grouped in a plurality of logic array blocks, said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks;

a plurality of first conductors associated with each of said blocks for selectively applying the outputs of the logic modules in the associated block to the inputs of the logic modules in that block;

a plurality of second conductors extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each group being associated with a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the associated row;

a plurality of third conductors extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each group being associated with a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the associated column;

means for selectively applying the output of each logic module to at least one of the second or third conductors in the group of second or third conductors associated with the block which includes that logic module;

means for selectively connecting each of said second conductors to at least one of said third conductors;

a plurality of fourth conductors associated with each of said blocks;

means for selectively connecting to each of the fourth conductors associated with each of said blocks any one of a multiplicity of said second or third conductors in the group of second or third conductors associated with that block; and

means for selectively connecting each of said fourth conductors associated with each of said blocks to the inputs of the logic modules in that block.

8. A programmable logic array integrated circuit comprising:

a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being disposed on said circuit in a two dimensional array;

a plurality of first conductors extending substantially parallel to a first dimension of said array;

a plurality of second conductors extending substantially parallel to a second dimension of said array;

an input pin associated with each of said first conductors;

first tri-state driver means associated with each of said first conductors, each of said first tri-state driver means being programmable to selectively apply to the associated first conductor a signal applied to the input pin associated with that first conductor;

a programmable switch associated with each of said logic modules for selecting as an output signal either the output of the associated logic module or the signal on one of said second conductors; and

second tri-state driver means associated with each of said programmable switches, each of said second tristate driver means being programmable to selectively apply the output signal of the associated programmable switch to one of said first conductors.

9. The circuit defined in claim 8 further comprising:

programmable memory means associated with each of said first and second tri-state driver means for controlling the associated tri-state driver means.

10. The circuit defined in claim 8 wherein each of said programmable switches is a multiplexer.

11. The circuit defined in claim 10 further comprising:

programmable memory means associated with each of said multiplexers for controlling the associated multiplexer.