Receiving circuit for demodulating an angle modulated signal

• US 5,260,671 A
• Filed: 05/15/1992
• Issued: 11/09/1993
• Est. Priority Date: 05/17/1991
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Iso, Yoshimi, Amada, Nobutaka, Noda, Masaki
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/883,466
• Time in Patent Office: 543 Days
• Field of Search: 329/300, 329/301, 329/302, 329/303, 329/304, 329/305, 329/306, 329/307, 329/308, 329/309, 329/310, 375/80, 375/81, 375/82, 375/84, 375/83, 375/85, 375/86, 375/87, 375/88, 375/89, 375/90, 375/91, 375/97, 375/98, 375/120, 331/22, 331/31, 331/23, 455/131, 455/202, 455/207, 455/209, 455/260, 455/314, 455/315, 455/316
• US Class Current: 329/302
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

A receiving circuit is designed for an MSK (Minimum Shift Keying) receiver and a QPSK (Quadrature Phase Shift Keying) receiver. The circuit provides a synchronous state determining device and a control voltage sweeping device for sweeping the output of a voltage oscillator. In the asynchronous state, a switch is turned off for interrupting a reproducing phase error signal so that the output of the voltage oscillator may be swept for causing the synchronous state. Then, the sweeping operation is stopped and the switch is turned on for controlling the voltage of the voltage controlled oscillator so that the low-frequency error component is removed from the phase error signal of the demodulating circuit. This results in implementing the simply-arranged demodulating circuit which keeps the proper demodulating performance against the shifted carrier frequency without any degrade and demodulates the input signal stably if the signal has a low C/N ratio. This circuit is capable of stably demodulating an MSK signal from a broadcasting satellite or a communication satellite.

Claims

1. A receiving circuit for receiving a suppressed carrier input signal, comprising:

coherent detecting means for coherently detecting said suppressed carrier input signal;

voltage controlled oscillating means for oscillating to said coherent detecting means as a recovered carrier;

phase error detecting means for detecting a phase error signal between said suppressed carrier input signal and said recovered carrier, wherein said voltage controlled oscillating means is controlled by said phase error signal;

synchronous state detecting means for detecting whether a carrier recovery phase locked loop circuit is in synchronous or asynchronous states, said carrier recovery phase locked loop including said coherent detecting means, said voltage controlled oscillating means and said phase error detecting means; and

controlling means for controlling said voltage controlled oscillating means depending on a low-frequency component level of said phase error signal, so that an operating point of said carrier recovery phase locked loop circuit moves toward the center when an output of said synchronous state detecting means indicates that said carrier recovery phase locked loop is in the asynchronous state.

2. A receiving circuit as claimed in claim 1, wherein said controlling means comprises:

a switch for intermittently breaking said phase error signal, wherein said switch is controlled by the output of said synchronous state detecting means;

a low-pass filter through which a low-frequency component of said phase error signal is passed;

an amplifier for amplifying said passed low-frequency component signal; and

an adder for adding said amplified signal to said phase error signal for controlling said voltage controlled oscillating means.

3. A receiving circuit as claimed in claim 1, wherein said controlling means comprises:

a low-pass filter through which a low-frequency component of said phase error signal is passed;

an A/D converter for converting said passed low-frequency component signal into a digital data signal;

an arithmetic processing means for arithmetically processing said A/D converted digital data signal;

a D/A converter for converting said processed digital data signal into an analog signal; and

an adder for adding said D/A converted analog signal to said phase error signal for controlling said voltage controlled oscillating means.

4. A receiving circuit as claimed in claim 3, further comprising:

sweeping means for sweeping the frequency oscillated by said voltage controlled oscillating means;

wherein said sweeping means is operated for performing a synchronous pull-in operation when the output of said synchronous state detecting means indicates the asynchronous state and stops said sweeping operation when said synchronous state detecting means detects the synchronous state.

5. A receiving circuit as claimed in claim 3, further comprising:

sweeping means for sweeping the frequency oscillated by said voltage controlled oscillating means;

wherein said sweeping means is operated for performing a synchronous pull-in operation when the output of said synchronous state detecting means indicates the asynchronous state and stops said sweeping operation when said synchronous state detecting means detects the synchronous state.

8. A receiving circuit as claimed in claim 2, wherein said controlling means comprises:

a low-pass filter through which a low-frequency component of said phase error signal is passed;

an A/D converter for converting said passed low-frequency component signal into a digital data signal;

an arithmetic processing means for arithmetically processing said A/D converted digital data signal;

a D/A converter for converting said processed digital data signal into an analog signal; and

an adder for adding said D/A converted analog signal to said phase error signal for controlling said voltage controlled oscillating means.

10. A receiving circuit as claimed in claim 8, further comprising:

sweeping means for sweeping the frequency oscillated by said voltage controlled oscillating means;

wherein said sweeping means is operated for performing a synchronous pull-in operation when the output of said synchronous state detecting means indicates the asynchronous state and stops said sweeping operation when said synchronous state detecting means detects the synchronous state.

6. A receiving circuit for receiving a suppressed carrier input signal used in a heterodyne receiver, comprising:

voltage controlled oscillating means for local oscillation;

mixing means for down-converting said suppressed carrier input signal into an intermediate frequency band;

down-converted coherent detecting means for coherently detecting said suppressed carrier input signal;

reference oscillating means for oscillating said intermediate frequency signal to said coherent detecting means as a recovered carrier;

phase error detecting means for detecting a phase error signal between said down-converted suppressed carrier input signal and said recovered carrier, wherein said voltage controlled oscillating means is controlled by said phase error signal;

synchronous state detecting means for detecting whether a carrier recovery phase locked loop circuit is in synchronous or asynchronous states, said carrier recovery phase locked loop including said voltage controlled oscillating means, said mixing means, said coherent detecting means, said reference oscillating means and said phase error detecting means; and

controlling means for controlling said voltage controlled oscillating means depending on a low-frequency component level of said phase error signal, so that an operating point of said carrier recovery phase locked loop circuit moves toward the center when an output of said synchronous state detecting means indicates that said carrier recovery phase locked loop is in the asynchronous state.

7. A receiving circuit as claimed in claim 6, wherein said controlling means comprises:

a switch for intermittently breaking said phase error signal, wherein said switch is controlled by the output of said synchronous state detecting means;

a low-pass filter through which a low-frequency component of said phase error signal is passed;

an amplifier for amplifying said passed low-frequency component signal; and

an adder for adding said amplified signal to said phase error signal for controlling said voltage controlled oscillating means.

9. A receiving circuit as claimed in claim 7, further comprising:

sweeping means for sweeping the frequency oscillated by said voltage controlled oscillating means;

wherein said sweeping means is operated for performing a synchronous pull-in operation when the output of said synchronous state detecting means indicates the asynchronous state and stops said sweeping operation when said synchronous state detecting means detects the synchronous state.

11. A receiving circuit for receiving a suppressed carrier input signal used in a heterodyne receiver, comprising:

first local oscillating means for first local oscillation;

first mixing means for down-converting said suppressed carrier input signal into a fist down-converted suppressed carrier input signal which occupies a first intermediate frequency band;

voltage controlled oscillating means for second local oscillation;

second mixing means for down-converting said first down-converted suppressed carrier input signal into a second down-converted suppressed carrier input signal which occupies a second intermediate frequency band;

coherent detecting means for coherently detecting said second down-converted suppressed carrier input signal;

reference oscillating means for oscillating a second intermediate frequency signal to said coherent detecting means as a recovered carrier;

phase error detecting means for detecting a phase error signal between said second down-converted suppressed carrier input signal and said recovered carrier, wherein said voltage controlled oscillating means is controlled by said phase error signal;

frequency variation detecting means for detecting a frequency variation from a desired frequency in an output of said voltage controlled oscillating means; and

controlling means for controlling said first local oscillating means depending on an output of said frequency variation detecting means, so that an oscillating frequency of said voltage controlled oscillating means is kept constant and said frequency variation from the desired frequency is approximately zero.

12. A receiving circuit as claimed in claim 11, wherein said frequency variation detecting means comprises:

second reference oscillating means for oscillating a reference frequency corresponding to said desired frequency; and

frequency comparing means for comparing an oscillating frequency of said voltage controlled oscillating means with an oscillating frequency of said second reference oscillating means;

wherein said controlling means controls said first local oscillating means depending on the compared information of said frequency comparing means.

13. A receiving circuit as claimed in claim 11, wherein said frequency variation detecting means comprises:

reference voltage supply means for supplying a reference voltage corresponding to said desired frequency; and

voltage comparing means for comparing a controlling voltage of said voltage controlled oscillating means with said reference voltage;

wherein said controlling means controls said first local oscillating means depending on the compared information of said voltage comparing means.

14. A receiving circuit as claimed in claim 11, further comprising:

means for restricting a control range of said first local oscillating means.

15. A receiving circuit as claimed in claim 14, further comprising:

means for stopping the control of said first local oscillating means when the oscillating frequency of said voltage controlled oscillating means is located near the center of a desired frequency.

16. A receiving circuit as claimed in claim 14, further comprising:

means for detecting a pseudo-locking state of said MSK demodulating circuit and means for restring the control of said first local oscillator during said pseudo-locking state.

17. A receiving circuit as claimed in claim 11, wherein a carrier recovery phase locked loop circuit comprising said voltage controlled oscillating means, said second mixing means, said coherent detecting means, said reference oscillating means and said phase error detecting means, is formed on one Si-semiconductor substrate;

and

an oscillating signal output terminal of said voltage controlled oscillating means is provided.

18. A receiving circuit as claimed in claim 11, wherein said first mixing means is a semiconductor integrated circuit formed on a GaAs half-insulated substrate.

19. A receiving circuit as claimed in claim 11, wherein said first mixing means comprises a semiconductor integrated circuit formed on a GaAs half-insulated substrate and a semiconductor substrate.

20. A receiving circuit as claimed in claim 11, wherein said suppressed carrier input signal is an MSK signal;

wherein said frequency variation detecting means comprises;

FM demodulating means for demodulating said MSK signal which is down-converted into said first intermediate frequency band by said first mixing means;

reference voltage supply means for supplying a reference voltage corresponding to said desired frequency; and

voltage comparing means for comparing an output voltage of said FM demodulating means with said reference voltage;

wherein said controlling means controls said first local oscillating means depending on the compared information of said voltage comparing means; and

wherein said FM demodulating means is used for demodulating a TV signal when a FM TV signal is received.

21. A receiving circuit for receiving a suppressed carrier input signal, comprising:

coherent detecting means for coherently detecting said suppressed carrier input signal;

voltage controlled oscillating means for oscillating to said coherent detecting means as a recovered carrier;

phase error detecting means for detecting a phase error signal between said suppressed carrier input signal and said recovered carrier, wherein said voltage controlled oscillating means is controlled by said phase error signal;

synchronous state detecting means for detecting whether a carrier recovery phase locked loop circuit is in synchronous or asynchronous states, said carrier recovery phase locked loop including said coherent detecting means, said voltage controlled oscillating means and said phase error detecting means; and

controlling means for controlling said voltage controlled oscillating means depending on a low-frequency component level of said phase error signal added to a ratio of said low-frequency component, so that an operating point of said carrier recovery phase locked loop circuit moves toward the center when an output of said synchronous state detecting means indicates that said carrier recovery phase locked loop is in the asynchronous state;

wherein said ratio of said low-frequency component is dependent on a result from said synchronous state detector.

22. A receiving circuit for receiving a suppressed carrier input signal used in a heterodyne receiver, comprising:

voltage controlled oscillating means for local oscillation;

mixing means for down-converting said suppressed carrier input signal into an intermediate frequency band;

down-converted coherent detecting means for coherently detecting said suppressed carrier input signal;

reference oscillating means for oscillating said intermediate frequency signal to said coherent detecting means as a recovered carrier;

phase error detecting means for detecting a phase error signal between said down-converted suppressed carrier input signal and said recovered carrier, wherein said voltage controlled oscillating means is controlled by said phase error signal;

synchronous state detecting means for detecting whether a carrier recovery phase locked loop circuit is in synchronous or asynchronous states, said carrier recovery phase locked loop including said voltage controlled oscillating means, said mixing means, said coherent detecting means, said reference oscillating means and said phase error detecting means; and

controlling means for controlling said voltage controlled oscillating means depending on a low-frequency component level of said phase error signal added to a ratio of said low-frequency component, so that an operating point of said carrier recovery phase locked loop circuit moves toward the center when an output of said synchronous state detecting means indicates that said carrier recovery phase locked loop is in the asynchronous state;

wherein said ratio of said low-frequency component is dependent on a signal from said synchronous state detector.

23. A receiving circuit for receiving a suppressed carrier input signal used in a heterodyne receiver, comprising:

first local oscillating means for first local oscillation;

first mixing means for down-converting said suppressed carrier input signal into a fist down-converted suppressed carrier input signal which occupies a first intermediate frequency band;

voltage controlled oscillating means for second local oscillation;

second mixing means for down-converting said first down-converted suppressed carrier input signal into a second down-converted suppressed carrier input signal which occupies a second intermediate frequency band;

coherent detecting means for coherently detecting said second down-converted suppressed carrier input signal;

reference oscillating means for oscillating a second intermediate frequency signal to said coherent detecting means as a recovered carrier;

phase error detecting means for detecting a phase error signal between said second down-converted suppressed carrier input signal and said recovered carrier, wherein said voltage controlled oscillating means is controlled by said phase error signal;

frequency variation detecting means for detecting a frequency variation form a desired frequency in an output of said voltage controlled oscillating means; and

controlling means for controlling said first local oscillating means depending on an output of said frequency variation detecting means added to a ratio of said frequency component, so that an oscillating frequency of said voltage controlled oscillating means is kept constant and said frequency variation from the desired frequency is approximately zero;

wherein said ratio of said frequency component is dependent on a signal from said frequency variation detecting means.

24. A receiving circuit as claimed in claim 23, wherein said frequency variation detecting means comprises:

second reference oscillating means for oscillating a reference frequency corresponding to said desired frequency; and

frequency comparing means for comparing an oscillating frequency of said voltage controlled oscillating means with an oscillating frequency of said second reference oscillating means;

wherein said controlling means controls said first local oscillating means depending on the compared information of said frequency comparing means.

25. A receiving circuit for receiving a radio frequency input signal, comprising:

down-converting means for down-converting said input signal into an intermediate frequency signal, wherein said down-converting means comprises a voltage controlled oscillator and a mixer;

coherent detecting means for coherently detecting said intermediate frequency signal, wherein said coherent detecting means comprises a second oscillator, and wherein said coherent detecting means outputs a first data signal corresponding to an in-phase component of said second oscillator and a second data signal corresponding to a 90 degree out-of-phase component of said second oscillator;

phase error detecting means for detecting a phase error signal between said intermediate frequency signal and an output signal of said second oscillator, wherein said voltage controlled oscillator is at least partially controlled by said phase error signal;

synchronous state detecting means for detecting whether a carrier recovery phase locked loop circuit is in synchronous or asynchronous states, said carrier recovery phase locked loop including said coherent detecting means, said voltage controlled oscillator and said phase error detecting means; and

controlling means for controlling said voltage controlled oscillator depending on a low-frequency component level of said phase error signal added to a ratio of said low-frequency component, so that an operating point of said carrier recovery phase locked loop circuit moves toward the center when an output of said synchronous state detecting means indicates that said carrier recovery phase locked loop is in the asynchronous state;

wherein said ratio of said low-frequency component is dependent on a result from said synchronous state detecting means.

26. A receiving circuit for receiving a radio frequency input signal, comprising:

down-converting means for down-converting said input signal into an intermediate frequency signal, wherein said down-converting means comprises a voltage controlled oscillator and a mixer;

coherent detecting means for coherently detecting said intermediate frequency signal, wherein said coherent detecting means comprises a second oscillator and wherein said coherent detecting means outputs a first detected signal corresponding to an in-phase component of said second oscillator and a second detected signal corresponding to a 90 degree out-of-phase component of said second oscillator;

phase error detecting means for detecting a phase error between said intermediate frequency signal and an output signal of said second oscillator from said first detected signal and said second detected signal and producing a phase error signal, wherein said voltage controlled oscillator is at least partially controlled by said phase error signal;

synchronous state detecting means for detecting whether a carrier recovery phase locked loop circuit is in synchronous or asynchronous states, said carrier recovery phase locked loop including said coherent detecting means, said voltage controlled oscillator and said phase error detecting means; and

correcting means for correcting the control signal of said voltage controlled oscillator, comprising;

biasing means for biasing said voltage controlled oscillator wherein said voltage controlled oscillator is caused to return to a center of an operable band of said down-converting means in the absence of a signal indicating the synchronous state;

phase error signal amplification means for amplifying a low-frequency component of said phase error signal;

adding means for adding said amplified low-frequency component signal with said phase error signal; and

switch means for enabling or disabling said adding operation, wherein said switch means is controlled by the output of said synchronous state detecting means;

wherein said voltage controlled oscillator is at least partially controlled by said phase error signal amplification means.