Dual pipe cache memory with out-of-order issue capability
First Claim
1. Cache memory apparatus for storing and loading data in a pipeline computer comprising, in combination:
- first memory means having a plurality of locations;
clock means providing sequential clock cycles;
instruction issue means for issuing an instruction stream containing store instructions for controlling storage of data in said first memory means and load instructions for controlling retrieval of data from said first memory means;
first cache control means connected to said instruction issue means and to said first memory means, said first cache control means being responsive to a load instruction issued by the instruction issue means to execute the load instruction at a load address in said first memory means, the load address representing a location in said first memory means from where data are to be retrieved under control of the corresponding load instruction, said first cache control means further being responsive to a store instruction issued by the instruction issue means and to a first clock cycle issued by said clock means to allocate a store cycle issued by said clock means to allocate a store address, the store address representing a location in said first memory means where data are to be stored under control of the corresponding store instruction; and
store history table means connected to said first cache control means and responsive to the allocation of a store address by said first cache control means to store a record of the store instruction issued by said instruction issue means, said record including the store address allocated by the first cache control means;
said first cache control means being responsive to said store history table means and to a second clock cycle subsequent to the first clock cycle to commit the store instruction at the corresponding allocated store address in said first memory means and said store history table means being responsive to the first cache control means committing a store instruction to clear the record of the committed store instruction.
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Accused Products
Abstract
A data cache memory apparatus permits load and store instructions to be issued out-of-order. The apparatus includes a memory. An instruction issue apparatus issues an instruction stream containing store and load instructions. The store instructions are completed in two passes, namely a store allocate pass and a corresponding store commit pass. A cache control is connected to the instruction issue apparatus and the memory and issues store and load addresses to the memory in response to instructions from the instruction issue apparatus. A store history table is connected to the cache control and stores a record of the addresses of the memory where data are to be stored, and thus a record of the store allocate passes issued by the instruction issue apparatus for which no corresponding store commit pass has been completed. The cache control responds to the subsequent corresponding store commit pass to issue the store address to the memory and to clear the store instruction from the store history table. If a load instruction designates an address for which a store allocate pass has issued but the corresponding store commit pass has not yet been issued, the cache control determines a conflict and the load instruction is reissued. Provision is made for retrieving data from a secondary cache and for clearing store instructions from the store history table upon detection of a branch error.
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Citations
26 Claims
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1. Cache memory apparatus for storing and loading data in a pipeline computer comprising, in combination:
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first memory means having a plurality of locations; clock means providing sequential clock cycles; instruction issue means for issuing an instruction stream containing store instructions for controlling storage of data in said first memory means and load instructions for controlling retrieval of data from said first memory means; first cache control means connected to said instruction issue means and to said first memory means, said first cache control means being responsive to a load instruction issued by the instruction issue means to execute the load instruction at a load address in said first memory means, the load address representing a location in said first memory means from where data are to be retrieved under control of the corresponding load instruction, said first cache control means further being responsive to a store instruction issued by the instruction issue means and to a first clock cycle issued by said clock means to allocate a store cycle issued by said clock means to allocate a store address, the store address representing a location in said first memory means where data are to be stored under control of the corresponding store instruction; and store history table means connected to said first cache control means and responsive to the allocation of a store address by said first cache control means to store a record of the store instruction issued by said instruction issue means, said record including the store address allocated by the first cache control means; said first cache control means being responsive to said store history table means and to a second clock cycle subsequent to the first clock cycle to commit the store instruction at the corresponding allocated store address in said first memory means and said store history table means being responsive to the first cache control means committing a store instruction to clear the record of the committed store instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. Cache memory apparatus for storing and loading data in a pipeline computer comprising, in combination:
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first memory means having a plurality of locations; clock means providing sequential clock cycles; instruction issue means for issuing an instruction stream containing store instructions to control storage of data in said first memory means and load instructions to control retrieval of data from said first memory means; first cache control means connected to said instruction issue means and to said first memory means, said first cache control means being responsive to a load instruction issued by the instruction issue means to execute the load instruction at a load address in said first memory means, the load address representing a location in said first memory means from where data are to be retrieved under control of the corresponding load instruction; and store history table means connected to said first cache control means and responsive to a store instruction issued by the instruction issue means and to said clock means to execute a store allocate pass during a first clock cycle and a separate store commit pass during a second clock cycle subsequent to the first clock cycle, said store history table storing a record of the store instruction during a store allocate pass, said record including a store address representing a location in said first memory means where data are to be stored under control of the corresponding store instruction; said first cache control means being responsive to a store instruction issued by said instruction issue means to operate said store history table means to execute said store allocate pass whereby the store address corresponding to the store instruction is reserved, said first cache control further being responsive to a store commit pass to execute the store instruction at the store address in said first memory means, said store history table means being responsive to the first cache control means executing a store instruction to clear the record of the executed store instruction. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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25. Instruction issue apparatus for conditionally issuing instructions to a cache memory of a pipeline computer comprising, in combination:
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instruction issue means for issuing an instruction stream containing a plurality of branches of store and load instructions; cache control means connected to said instruction issue means and to said cache memory for allocating store addresses representing locations in said cache memory where data are to be stored and load addresses representing locations in said cache memory from where data are to be retrieved, said cache control means further including branch test means for determining whether a branch of instructions is a correct branch or a branch error; and store history table means connected to said cache control means and to said instruction issue means and responsive to a store instruction from the instruction issue means to store a record of the store instruction issued by said instruction issue means, said record including the store address of said cache memory where data are to be stored under control of the corresponding store instruction; said store history table means being further responsive to said branch test means determining a branch error condition to clear store instruction records from said store history table means. - View Dependent Claims (26)
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Specification