×

Dual pipe cache memory with out-of-order issue capability

  • US 5,261,071 A
  • Filed: 03/21/1991
  • Issued: 11/09/1993
  • Est. Priority Date: 03/21/1991
  • Status: Expired due to Fees
First Claim
Patent Images

1. Cache memory apparatus for storing and loading data in a pipeline computer comprising, in combination:

  • first memory means having a plurality of locations;

    clock means providing sequential clock cycles;

    instruction issue means for issuing an instruction stream containing store instructions for controlling storage of data in said first memory means and load instructions for controlling retrieval of data from said first memory means;

    first cache control means connected to said instruction issue means and to said first memory means, said first cache control means being responsive to a load instruction issued by the instruction issue means to execute the load instruction at a load address in said first memory means, the load address representing a location in said first memory means from where data are to be retrieved under control of the corresponding load instruction, said first cache control means further being responsive to a store instruction issued by the instruction issue means and to a first clock cycle issued by said clock means to allocate a store cycle issued by said clock means to allocate a store address, the store address representing a location in said first memory means where data are to be stored under control of the corresponding store instruction; and

    store history table means connected to said first cache control means and responsive to the allocation of a store address by said first cache control means to store a record of the store instruction issued by said instruction issue means, said record including the store address allocated by the first cache control means;

    said first cache control means being responsive to said store history table means and to a second clock cycle subsequent to the first clock cycle to commit the store instruction at the corresponding allocated store address in said first memory means and said store history table means being responsive to the first cache control means committing a store instruction to clear the record of the committed store instruction.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×