Method and apparatus for providing down-loaded instructions for execution by a peripheral controller

• US 5,261,114 A
• Filed: 11/09/1990
• Issued: 11/09/1993
• Est. Priority Date: 11/09/1990
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: AST Research, Inc. (Samsung Group)
• Inventors: Raasch, Charles F., Kim, Jason S. M.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/612,425
• Time in Patent Office: 1,096 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/500, 395/800, 395/375
• US Class Current: 709/221
• CPC Class Codes: G06F 13/105 where the programme performs an input/output emulation function
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for downloading instructions and other information to a peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system which downloads instructions from the ISA compatible computer to an random access memory (RAM) accessible by the peripheral controller. The peripheral controller then executes these instructions to emulate the functions of conventional INTEL 8042 and 8742 series integrated circuits. The peripheral controller also provides other features not provided by the conventional 8042 or 8742 by executing other downloaded instructions located in the RAM.

Claims

1. A peripheral controller for use with a host IBM-AT compatible computer system, said peripheral controller having a core microprocessor said peripheral controller performing input and output functions for said host, said peripheral controller comprising:

a random access memory (RAM) coupled to said core microprocessor, said RAM configured such that instructions located in said RAM are accessible for execution by said core microprocessor, said RAM configured to receive down-loaded instructions from said host;

a boto indicator which provides an active signal when said RAM is receiving said down-loaded instructions from said host;

an address counter having outputs coupled to said RAM to provide addressing for said RAM;

means for receiving said down-loaded instructions from said host and for transferring said down-loaded instructions to said RAM at an address location selected by said address counter; and

a microprocessor reset indicator coupled to said core microprocessor, said microprocessor reset indicator responsive to said boot indicator to maintain said core microprocessor in a reset state while said RAM receives said down-loaded instructions.

2. The peripheral controller of claim 1, wherein said means for receiving comprises a RAM controller having first and second sets of address inputs, first and second sets of data inputs, RAM address outputs coupled to address inputs to said RAM, and RAM data outputs coupled to data inputs to said RAM, said RAM controller responsive to said boot indicator to select under host control the first or the second set of address inputs for transmission to said RAM address outputs and to select under host control the first or the second set of data inputs for transmission to said RAM data outputs, and said RAM controller also receiving data from said RAM for transmission to said host.

3. The peripheral controller of claim 2, wherein said RAM control inputs comprise:

a RAM write enable signal;

a RAM output enable signal; and

at least one RAM chip select signal to activate selected portions of said RAM.

4. The peripheral controller of claim 3, wherein said address counter is implemented in hardware to provide addresses for accessing consecutive memory locations in said RAM.

5. The peripheral controller of claim 4, wherein said address counter is implemented as an integrated circuit which provides addresses for accessing consecutive memory locations in said RAM.

6. The peripheral controller of claim 3, wherein said down-loaded instructions comprises instructions which modify functions previously implemented by instructions stored in said RAM.

7. A peripheral controller for use with a host IBM-AT compatible computer system, said peripheral controller having a core microprocessor said peripheral controller performing input and output functions for said host, said peripheral controller comprising:

a random access memory (RAM) coupled to said core microprocessor, said core microprocessor capable of executing instructions located in said RAM, said RAM configured to receive down-=loaded instruction from said host for execution by said core microprocessor;

a boot indicator responsive to the host'"'"'s sending down-loaded instructions to said RAM, said host indicator providing an active signal when said RAM is receiving said down-loaded instructions from said host;

a RAM controller, said RAM controller having first and second sets of data inputs, and first address inputs from an address counter and second address inputs from said core microprocessor, said RAM controller responsive to an active signal on said boot indicator to select said first set of data inputs, sand said first set of address inputs, for transmission to a set of RAM data outputs and RAM address outputs connected to data inputs and address inputs of said RAM; and

a microprocessor reset indicator coupled to said core microprocessor and responsive to an active signal on said boot indicator to maintain said core microprocessor in a reset state while said RAM receives said down-loaded instructions from said host.

8. The peripheral controller of claim 7, wherein said RAM controller further comprises RAM control inputs comprising:

a RAM write enable signal;

a RAM output enable signal; and

at least one RAM chip select signal to activate selected portions of said RAM.

9. The peripheral controller of claim 8, wherein said address counter is implemented in hardware to provide addresses for accessing consecutive memory locations in said RAM.

10. The peripheral controller of claim 9, wherein said address counter is implemented as an integrated circuit which provides addresses for accessing consecutive memory locations in said RAM.

11. The peripheral controller of claim 8, wherein said down-loaded instructions comprise instructions which modify functions previously implemented by instructions stored in said RAM.

12. A method of down-loading instructions to a random access memory (RAM) in a peripheral controller, said peripheral controller for use with a host IBM-AT compatible computer system (host) having a data bus, said RAM having a plurality of addressable storage locations and a plurality of address lines for accessing said addressable storage locations, said peripheral controller having a core microprocessor capable of executing said instructions located in said RAM, said peripheral controller also having a RAM controller for selecting a plurality of potential inputs to said RAM controller for transmission through said RAM controller to said RAM, said peripheral controller performing input and output functions for said host, said method comprising the steps of:

initializing an address counter having outputs, said outputs coupled as a first set of address inputs to said RAM controller;

selecting said first set of address inputs for transmission through said RAM controller to address inputs of said RAM such that signals on said address counter are transmitted to said RAM;

activating a boot indicator which provides an active signal to said peripheral controller when said RAM is receiving said instructions from said host;

activating a microprocessor reset indicator to maintain said core microprocessor in a reset condition while said RAM receives said instructions from said host;

selecting signals on said data bus from said host for transmission to said RAM;

executing write commands from said host to said peripheral controller, said write commands providing said instructions for said RAM;

automatically incrementing said address counter to address additional storage locations in said RAM;

activating a down-load terminated indicator upon completion of down-loading operations;

selecting said second set of address inputs for transmission through said RAM controller for transmission to said RAM; and

selecting said second set of data inputs for transmission through said RAM controller for transmission to said RAM.

13. A peripheral controller for use with a host IBM-AT compatible computer system (host), said peripheral controller having a core microprocessor executing instructions located in a random access memory (RAM) during operation of said peripheral controller in a first mode, said peripheral controller also operable in a second mode during which said core microprocessor remains in a reset state and said host down-loads instructions to said RAM, said peripheral controller performing input and output functions for said host in said first mode, said peripheral controller comprising:

a RAM controller having a first and a second set of address inputs and a first and a second set of data inputs, said RAM controller coupling said first set of address inputs and said first set of data inputs to said RAM while said peripheral controller operates in said second mode in order to receive down-loaded instructions from said host, said down-loaded instructions comprising either a replacement set of instructions allowing said peripheral controller to perform a set of input and output functions, or a modification set of instructions which modifies functions previously implemented by instructions or which allows said peripheral controller to perform additional input or output functions.