Direct application of unpackaged integrated circuit to flexible printed circuit

• US 5,261,593 A
• Filed: 08/19/1992
• Issued: 11/16/1993
• Est. Priority Date: 08/19/1992
• Status: Expired due to Term

• Current Assignee: Multek Flexible Circuits, Inc. (Flex, Ltd.)
• Original Assignee: Sheldahl, Inc.
• Inventors: Casson, Keith L., Selbitschka, Eugene T., Habeck, Kelly D.
• Primary Examiner(s): Heinrich, Samuel M.
• Application Number:
  US07/932,064
• Time in Patent Office: 454 Days
• Field of Search: 228/180.1, 228/180.2, 228/201, 228/232, 228/239, 228/240, 228/248
• US Class Current: 228/180.22
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/10992 : Using different connection materials, e.g. different solders, for the same connection
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3485 : Applying solder paste, slurry or powder thick film methods for applying conductive paste or ink patterns H05K3/12
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A method is described for electrically connecting flip chips to a flexible printed circuit substrate. The method comprises (1) providing solder paste to a plurality of active contact pads located on the flexible printed circuit substrate, (2) placing the flip chips on the substrate such that solder bumps located on the flip chips are in registration with the solder paste on the active contact pads, and (3) heating the resulting assembly as a whole so that the solder paste on each active contact pad reflows to form an electrical connection with its corresponding solder bump.

Claims

1. A method for electrically connecting a plurality of flip chips, each flip chip having two or more solder bumps, to a flexible printed circuit substrate having a plurality of contact pads, the method comprising the steps of:

providing solder paste on a plurality of active contact pads on the flexible printed circuit substrate, each active pad having a corresponding solder bump on one of the plurality of flip chips, such that the solder paste on each active contact pad is of sufficient volume to facilitate an electrical connection between the active contact pad and the corresponding solder bump;

placing the chips on the substrate to form an unsoldered chip-substrate assembly, such that the solder paste on each active contact pad is in registration with the corresponding solder bump; and

heating the chip-substrate assembly as a whole with a heating means which operates by direct infrared radiation of the assembly or by transmission of heat to the assembly from a heated working fluid, such that the solder paste on each active contact pad reflows to form an electrical connection with the corresponding solder bump.

2. The method of claim 1, wherein the plurality of flip chips are unpackaged silicon chips having a passivation layer on an active side of the chips for protecting active devices located on the chips from environmental contaminants, and having solder bumps located on bonding pads located on the active side.

3. The method of claim 1, wherein the flexible printed circuit substrate is an adhesiveless flexible polyimide copper laminate

4. The method of claim 1, wherein the flexible printed circuit substrate is an adhesiveless flexible polyester laminate.

5. The method of claim 1, wherein the flexible printed circuit substrate is an adhesive-based laminate.

6. The method of claim 1, wherein each of the solder bumps is comprised of:

an electroplated copper pedestal attached to an active side of the flip chip; and

tin-lead solder having a tin content of between 3% and 10%, the tin-lead solder being hemispherically-shaped and attached to the copper pedestal such that the copper pedestal is substantially between the solder and the flip chip.

7. The method of claim 6, wherein the tin-lead solder is comprised of 6% tin and 94% lead and has a reflow point in the range of 316°

C.

8. The method of claim 1, wherein the solder paste is comprised of solder particles in a carrier matrix of flux, the solder paste having 90% solder particles and 10% flux and having a viscosity of 700 kcps, and wherein the solder particles are comprised of a 63% tin, 35% lead and 2% silver eutectic alloy, formed into substantially spherically-shaped objects having a diameter less than 45 microns, and having a reflow point of in the range of 182°

C.

9. The method of claim 1, wherein the solder paste is comprised of solder particles in a carrier matrix of flux, the solder paste having 90% solder particles and 10% flux and having a viscosity of 900 kcps, and wherein the solder particles are comprised of a 63% tin and 37% lead eutectic alloy, formed into substantially spherically-shaped objects having a diameter less than 45 microns, and having a reflow point of in the range of 183°

C.

10. The method of claim 1, wherein the solder paste is comprised of solder particles in a carrier matrix of flux, the solder particles comprised of high temperature tin-lead solder having a tin content of between 3% and 10%.

11. The method of claim 1, wherein the providing solder paste step comprises stenciling the solder paste on the active contact pads on the substrate through a stencil having etched openings corresponding to the pads.

12. The method of claim 11, wherein the stencil is made of brass and has a thickness of 4 mils, and wherein the etched openings have a diameter of 14 mils.

13. The method of claim 11, wherein the solder paste is stencilled through the stencil and on the active contact pads by an automated stencilling machine having a round squeegee of 90 durometer hardness, the squeegee moving at 1.5 inches/second and applying a force of 22 psi.

14. The method of claim 1, wherein the providing solder paste step includes providing a volume of the solder paste, such that the volume of solder paste located on each active contact pad is optimized as a function of the area of the pad, the connected distance between the substrate and the corresponding flip chip, and the volume of the corresponding solder bump.

15. The method of claim 14, wherein the providing solder paste step includes providing 6×

10^-7 cubic inches of solder paste on each active contact pad.

16. The method of claim 1, wherein the placing step comprises placing the chips on the substrate using an optical placement means.

17. The method of claim 1, wherein the heating means is from the group of:

an infrared reflow oven, a vapor phase reflow oven, or a convection reflow oven.

18. The method of claim 17, wherein the heating means is an infrared reflow oven having a nitrogen purge option for inhibiting formation of solder oxides during the heating step.

19. The method of claim 18, wherein the heating step includes heating the assembly according to a temperature profile, the temperature profile comprised of

a first preheat zone for raising the temperature of the assembly from an ambient temperature to approximately 20°

-30°

C. below the reflow point of the solder paste;

a second preheat zone for raising the temperature of the assembly to just below the reflow point of the solder paste;

a reflow zone for raising the temperature of the assembly to approximately 40°

C. above the reflow point of the solder paste; and

a cooling zone for allowing the assembly to cool to ambient temperature.

20. The method of claim 19, wherein the assembly is moved through the oven at a rate of 32.4 inches/minute, and wherein the temperature of the assembly rises at a rate less than 2°

C./second in the first preheat, second preheat, and reflow zones.

21. The method of claim 1, wherein the heating step includes forming the electrical connection of each of the chips to the substrate simultaneously

22. The method of claim 1, further comprising the step of coating the assembly with a low stress epoxy encapsulant after heating the chip-substrate assembly

23. The method of claim 1, further comprising the step of cleaning the assembly using freon-based solvents and ultrasound processes.

24. The method of claim 1, wherein the plurality of contact pads are located on both sides of the flexible printed circuit substrate and the plurality of flip chips are electrically connected to both sides of the flexible printed circuit substrate.

25. A method for electrically connecting a plurality of flip chips to a flexible printed circuit substrate having a plurality of contact pads located on either side of the substrate, each flip chip an unpackaged silicon chip having a passivation layer on an active side of the chips for protecting active devices located on the chips from environmental contaminants, and having two or more solder bumps located on bonding pads located on the active side, each solder bump comprised of an electroplated copper pedestal attached to the active side of the flip chip and tin-lead solder having 6% tin and 94% lead and having a reflow point in the range of 316°

C., the tin-lead solder being hemispherically-shaped and attached to the copper pedestal such that the copper pedestal is substantially between the solder and the flip chip, the flexible printed circuit substrate comprised of an adhesiveless flexible polyimide copper laminate, the method comprising the steps of;

providing solder paste on a plurality of active contact pads on the flexible printed circuit substrate by stenciling the solder paste on the active contact pads on the substrate through a 4 mil thick brass stencil having 14 mil diameter etched openings corresponding to the pads, using an automated stencilling machine having a round squeegee of 90 durometer hardness, the squeegee moving at 1.5 inches/second and applying a force of 22 psi, the solder paste comprised of solder particles in a carrier matrix of flux, the solder paste having 90% solder particles and 10% flux and having a viscosity of 900 kcps, the solder particles comprised of a 63% tin and 37% lead eutectic alloy, formed into substantially spherically-shaped objects having a diameter less than 45 microns, and having a reflow point in the range of 183°

C., each active pad having a corresponding solder bump on one of the plurality of flip chips, such that the solder paste on each active contact pad is of sufficient volume to facilitate an electrical connection between the active contact pad and the corresponding solder bump;

placing the chips on the substrate to form an unsoldered chip-substrate assembly using an optical placement means, such that the solder paste on each active contact pad is in registration with the corresponding solder bump;

heating the chip-substrate assembly as a whole with a heating means comprised of passing the assembly through an infrared reflow oven having a nitrogen purge option for inhibiting formation of solder oxides, at a rate of 32.4 inches/minute, and such that the temperature of the assembly rises at a rate less than 2°

C./second, the heating performed in accordance with a temperature profile comprised of;

a first preheat zone for raising the temperature of the assembly from an ambient temperature to approximately 20°

-30°

C. below the reflow point of the solder paste;

a second preheat zone for raising the temperature of the assembly to just below the reflow point of the solder paste;

a reflow zone for raising the temperature of the assembly to approximately 40°

C. above the reflow point of the solder paste; and

a cooling zone for allowing the assembly to cool to ambient temperature;

such that the solder paste on each active contact pad reflows to form an electrical connection with the corresponding solder bump;

cleaning the assembly using freon-based solvents and ultrasound processes; and

coating the assembly with a low stress epoxy encapsulant.