IGBT process to produce platinum lifetime control
First Claim
1. An improved fabrication process for making a MOS-type insulated gate controlled four-layer power switching device, the process comprising:
- forming a semiconductor substrate having a first layer of a first dopant type defining a device anode and second layer of a second, opposite-polarity dopant type defining a drain region extending from an upper surface of the substrate toward the first layer;
forming an insulative layer on the upper surface of the second layer of the substrate and an insulated gate contact layer on the insulative layer;
forming double diffused regions including a body region of the first dopant type and a source region of the second dopant type within the body region, the body region forming two PN junctions with the drain and source regions, respectively spaced apart so as to define a channel region in the body region subjacent the insulated gate contact;
forming a source contact alongside the gate contact but spaced insulatively therefrom, the source contact forming an electrical connection to the source region and the body region and a short therebetween and defining a cathode contact for the device;
forming a anode contact on the opposite side of the substrate in electrical connection to the first layer;
the step of forming the second layer including;
forming a first portion contacting the first layer and having a first thickness and a first doping concentration;
forming a second portion contacting the second layer and extending to said upper surface to receive said double diffused regions;
sizing and doping the second portion to a second thickness and a second doping concentration sufficient to block a predetermined maximum reverse bias voltage; and
sizing and doping the first portion to produce a predetermined output impedance (R0) sufficient to resist current flow during forward conduction when a high voltage (Vce) is across the cathode and anode contacts.
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Accused Products
Abstract
For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (˜1014 /cm3) to block reverse bias voltage. The N+ layer is >20 μm thick and doped below ˜1017 /cm3 but above the N- doping to enhance output impedance and reduce gain at high Vce conditions. Or the N+ layer is formed with a thin (˜5 μm) highly doped (>1017 /cm3) layer and a thick (>20 μm) layer of ˜1016 /cm3 doping. A platinum dose of 1013 to ˜1016 /cm2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si-H into the film.
157 Citations
84 Claims
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1. An improved fabrication process for making a MOS-type insulated gate controlled four-layer power switching device, the process comprising:
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forming a semiconductor substrate having a first layer of a first dopant type defining a device anode and second layer of a second, opposite-polarity dopant type defining a drain region extending from an upper surface of the substrate toward the first layer; forming an insulative layer on the upper surface of the second layer of the substrate and an insulated gate contact layer on the insulative layer; forming double diffused regions including a body region of the first dopant type and a source region of the second dopant type within the body region, the body region forming two PN junctions with the drain and source regions, respectively spaced apart so as to define a channel region in the body region subjacent the insulated gate contact; forming a source contact alongside the gate contact but spaced insulatively therefrom, the source contact forming an electrical connection to the source region and the body region and a short therebetween and defining a cathode contact for the device; forming a anode contact on the opposite side of the substrate in electrical connection to the first layer; the step of forming the second layer including; forming a first portion contacting the first layer and having a first thickness and a first doping concentration; forming a second portion contacting the second layer and extending to said upper surface to receive said double diffused regions; sizing and doping the second portion to a second thickness and a second doping concentration sufficient to block a predetermined maximum reverse bias voltage; and sizing and doping the first portion to produce a predetermined output impedance (R0) sufficient to resist current flow during forward conduction when a high voltage (Vce) is across the cathode and anode contacts. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An improved fabrication process for making a MOS-type insulated gate controlled four-layer power switching device, the process comprising:
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forming a semiconductor substrate having a first layer of a first dopant type defining a device anode and second layer of a second, opposite-polarity dopant type defining a drain region extending from an upper surface of the substrate toward the first layer; forming an insulative layer on the upper surface of the second layer of the substrate and an insulated gate contact layer on the insulative layer; forming double diffused regions including a body region of the first dopant type and a source region of the second dopant type within the body region, the body region forming two PN junctions with the drain and source regions, respectively spaced apart so as to define a channel region in the body region subjacent the insulated gate contact; forming a source contact alongside the gate contact but spaced insulatively therefrom, the source contact forming an electrical connection to the source region and the body region and a short therebetween and defining a cathode contact for the device; forming a anode contact on the opposite side of the substrate in electrical connection to the first layer; and performing a minority carrier lifetime control procedure including; providing a transition metal having a deep level in silicon suitable for recombination; determining a maximum dose of the selected transition metal that can be fully dissolved into the substrate at a temperature in a range between a eutectic temperature of the substrate and an annealing temperature of the substrate; depositing a predetermined dose of the transition metal less than the maximum dose and then diffusing the metal atoms throughout the substrate at a temperature within said range. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. In a fabrication process for making a semiconductor power device having at least one PN junction, an improved minority carrier lifetime control process comprising:
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selecting a transition metal having a deep level in silicon suitable for recombination; determining a maximum dose of the selected transition metal that can be fully dissolved into the substrate at a temperature in a range between a eutectic temperature of the substrate and an annealing temperature of the substrate; determining and depositing a dose of the transition metal not exceeding the maximum dose sufficient to effect lifetime control without substantially increasing leakage current of the device; and diffusing the metal atoms in the substrate at a temperature within said range; the depositing step including forming a silicide layer of the transition metal on the substrate and stripping away excess deposited transition metal to produce a dose of the transition metal less than the maximum dose. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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44. An improved fabrication process for making a MOS-type insulated gate controlled power switching device, the process comprising:
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forming a semiconductor substrate having an upper surface and a lower surface and including one or more layers defining a drain region of a first dopant type extending from the upper surface toward the lower surface of the substrate; forming an insulative layer on the upper surface of the substrate and an insulated gate contact layer on the insulative layer; forming double diffused regions including a body region of a second, opposite dopant type and a source region of the first dopant type within the body region, the body region forming two PN junctions with the drain and source regions, respectively spaced apart so as to define a channel region in the body region subjacent the insulated gate contact; forming a source contact layer alongside the gate contact but spaced insulatively therefrom, the source contact forming an electrical connection to the source region and the body region and a short therebetween and defining a source or cathode contact for the device; and forming a drain or anode contact on the lower surface of the substrate; the insulated gate contact layer and the source contact layer being patterned to form a plurality of complementary, parallel interdigitated gate and source fingers and a gate bus interconnecting the gate fingers; the body and source regions extending lengthwise along opposite margins of the gate fingers and gate bus, the body regions being spaced at a first lateral spacing L1 beneath the gate fingers across the drain region of a first dopant type and being spaced at a second spacing L2 beneath the gate bus greater than the first spacing L1 and forming a first breakdown prone region; the process further including doping at least a portion of the first breakdown prone region with dopant of the second dopant type over a lateral extent effective to interconnect the source regions beneath the gate bus and neutralize a portion of the channel region adjoining the interconnection. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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61. An improved fabrication process for making a MOS-type insulated gate controlled power switching device, the process comprising:
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forming a semiconductor substrate having an upper surface and a lower surface and including one or more layers defining a drain region of a first dopant type extending from the upper surface toward the lower surface of the substrate; forming an insulative layer on the upper surface of the substrate and an insulated gate contact layer on the insulative layer; forming double diffused regions including a body region of a second, opposite dopant type and a source region of the first dopant type within the body region, the body region forming two PN junctions with the drain and source regions, respectively spaced apart so as to define a channel region in the body region subjacent the insulated gate contact; forming a source contact layer alongside the gate contact but spaced insulatively therefrom, the source contact forming an electrical connection to the source region and the body region and a short therebetween and defining a source or cathode contact for the device; forming a drain or anode contact on the lower surface of the substrate; and depositing a dielectric film on the upper surface of the substrate, including selecting a dielectric composition and controlling deposition thereof to produce a film that is substantially nonpolarizable under high voltage conditions and forms an effective mobile ion and moisture barrier. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84)
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Specification