×

IGBT process to produce platinum lifetime control

  • US 5,262,336 A
  • Filed: 03/13/1992
  • Issued: 11/16/1993
  • Est. Priority Date: 03/21/1986
  • Status: Expired due to Term
First Claim
Patent Images

1. An improved fabrication process for making a MOS-type insulated gate controlled four-layer power switching device, the process comprising:

  • forming a semiconductor substrate having a first layer of a first dopant type defining a device anode and second layer of a second, opposite-polarity dopant type defining a drain region extending from an upper surface of the substrate toward the first layer;

    forming an insulative layer on the upper surface of the second layer of the substrate and an insulated gate contact layer on the insulative layer;

    forming double diffused regions including a body region of the first dopant type and a source region of the second dopant type within the body region, the body region forming two PN junctions with the drain and source regions, respectively spaced apart so as to define a channel region in the body region subjacent the insulated gate contact;

    forming a source contact alongside the gate contact but spaced insulatively therefrom, the source contact forming an electrical connection to the source region and the body region and a short therebetween and defining a cathode contact for the device;

    forming a anode contact on the opposite side of the substrate in electrical connection to the first layer;

    the step of forming the second layer including;

    forming a first portion contacting the first layer and having a first thickness and a first doping concentration;

    forming a second portion contacting the second layer and extending to said upper surface to receive said double diffused regions;

    sizing and doping the second portion to a second thickness and a second doping concentration sufficient to block a predetermined maximum reverse bias voltage; and

    sizing and doping the first portion to produce a predetermined output impedance (R0) sufficient to resist current flow during forward conduction when a high voltage (Vce) is across the cathode and anode contacts.

View all claims
  • 5 Assignments
Timeline View
Assignment View
    ×
    ×