Tester calibration procedure which includes fixturing

• US 5,262,716 A
• Filed: 04/21/1992
• Issued: 11/16/1993
• Est. Priority Date: 04/21/1992
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Gregory, Walter L. Jr., Glasgow, Davis M., Stepleton, Jay M., Lannen, Kay C.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US07/871,430
• Time in Patent Office: 574 Days
• Field of Search: 324/158 R, 324/73.1, 324/158 F, 324/158 P
• US Class Current: 324/750.02
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A system and method for calibrating testers. A reference timing signal and an internal timing signal used in tester calibration are generated within a tester. A first calibration is performed wherein test module channel characteristics are measured and recorded, and an adjustment value is determined to correct the time placement of the internal timing signal. Driver and receiver delays are adjusted based on the characteristics measured in this first calibration, and the internal timing signal is adjusted as well. A second calibration is performed wherein temporal relationships between the adjusted internal timing signal and signals at the test module channel mint pins are determined. Driver and receiver delays are adjusted based on the results of this calibration. An optional calibration is performed wherein temporal relationship between the adjusted internal timing signal and signals at the board-interface end of a test fixture are measured. Using these measurements and the measurements obtained in the second calibration, a test fixture characterization is performed and recorded. Delays of the drivers and receivers are again adjusted to account for the fixture characteristics. Additional calibration methods provided by the present invention include a manual multi-module calibration to keep test module channels aligned when a new module is designated as the master module, and a manual synchronization clock calibration to deskew drivers and receivers relative to an external clock supplied by the device under test.

Claims

1. A system for calibrating testers comprising:

(a) a signal generator for generating an internal timing signal;

(b) at least one test module connected to said signal generator for interfacing to a device under test;

(c) a test probe for receiving test signals at various locations;

(d) a time measurement device, connected to said signal generator, for measuring the time difference between edges of a signal generated by said signal generator and edges of test signal received by said test probe;

(e) a probe interface channel, connected to said test probe and to said time measurement device, for receiving test signals from said test probe; and

(f) wherein said test module comprises a plurality of test-module channels for sending signals to and receiving signals from a device under test.

2. The system of claim 1, further comprising a second signal generator, connected to said signal generator, for generating a reference timing signal at an output port of one of said test modules.

3. The system of claim 1 further comprising a user interface, connected to said test module, configured to prompt users for inputs.

4. The system of claim 2 further comprising a user interface, connected to said test module, configured to prompt users for inputs.

5. The system of claim 1 further comprising a storage device for storing values determined by said test modules, said storage device connected to said test modules.

6. The system of claim 2 further comprising a storage device for storing values determined by said test modules, said storage device connected to said test modules.

7. The system of claim 1, wherein said test-module channels comprise:

drivers for sending signals to the device under test;

receivers for receiving signals from the device under test; and

independent delay means for adjusting the timing of said signals sent to and received by said drivers and receivers, respectively.

8. The system of claim 2, wherein said test-module channels comprise:

drivers for sending signals to the device under test;

receivers for receiving signals from the device under test; and

independent delay means for adjusting the timing of said signals sent and received by said drivers and receivers, respectively.

9. The system of claim 7, wherein said probe interface channel comprises:

a probe receiver for receiving said test signals from said test probe; and

second independent delay means, coupled to said probe receiver, for adjusting the timing of said received test signals.

10. The system of claim 8, wherein said probe interface channel comprises:

a probe receiver for receiving said test signals from said test probe; and

second independent delay means, coupled to said probe receiver, for adjusting the timing of said received test signals.

11. The system of claim 1, wherein said signal generator is of the phase-locked loop type, capable of being adjusted by an input signal.

12. The system of claim 1, further comprising:

first means for characterizing at least one of said test-module channels using a time-target signal and an internal timing signal, wherein said internal timing signal is generated by said signal generator;

second means, coupled to said first means, for determining a time measurement value, wherein said time measurement value is used to adjust said internal timing signal;

third means, coupled to said second means, for determining individual time values necessary to synchronize at least one of said test-module channels, wherein said determination is based on a temporal relationship between said internal timing signal and signals at test-module mint pins; and

fourth means, coupled to said third means for adjusting said test modules based on said individual time values.

13. The system of claim 12, further comprising fifth means, coupled to said third means, for recording said individual time values.

14. The system of claim 12, wherein said second means further comprises fifth means for performing a reference calibration to obtain a target time value measurement based on a temporal relationship between a signal representing a reference signal from a device under test and said internal timing signal.

15. The system of claim 14, wherein said fifth means comprises:

means for characterizing test modules and said internal timing signal in response to time interval measurements between said internal timing signal and said signal representing a reference signal from a device under test;

means for providing characterized parameters as a result of said characterization;

means for adjusting test module timing and a temporal position of said internal timing signal based on said characterized parameters; and

means for recording said characterized parameters.

16. The system of claim 12, wherein said fourth means comprises means for adjusting an amount of delay introduced in said test-module channels.

17. The system of claim 12, further comprising:

a calibration fixture having a plurality of fixture paths and fixture nails;

means for measuring temporal relationships between said internal timing signal and a signal representing said internal timing signal at said fixture nails to characterize time delays through at least one of said fixture paths; and

means for adjusting said test modules in response to said temporal relationships between said internal timing signal and a signal at said fixture nails.